| Message ID | ef3f942c1d933ef757a0de84c2890d6779471239.1717755404.git.shravankr@nvidia.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Updates to mlxbf-pmc | expand |
On Fri, 7 Jun 2024, Shravan Kumar Ramani wrote: > Document newly added "count_clock" and "use_odd_counter" sysfs entries > for the Mellanox BlueField PMC driver. > > Signed-off-by: Shravan Kumar Ramani <shravankr@nvidia.com> > Reviewed-by: David Thompson <davthompson@nvidia.com> > --- > .../ABI/testing/sysfs-platform-mellanox-pmc | 23 +++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/Documentation/ABI/testing/sysfs-platform-mellanox-pmc b/Documentation/ABI/testing/sysfs-platform-mellanox-pmc > index 9f987c6410da..ee03d066c0d9 100644 > --- a/Documentation/ABI/testing/sysfs-platform-mellanox-pmc > +++ b/Documentation/ABI/testing/sysfs-platform-mellanox-pmc > @@ -52,3 +52,26 @@ Description: > Writing 0 to the sysfs will clear the counter, writing any other > value is not allowed. > > +What: /sys/bus/platform/devices/<HID>/hwmon/hwmonX/<block>/count_clock > +Date: May 2024 > +KernelVersion: 6.10 > +Contact: "Shravan Kumar Ramani <shravankr@nvidia.com>" > +Description: > + Use a counter for counting cycles. This is used to repurpose/dedicate > + any of the counters in the block to counting cycles. Each counter is > + represented by a bit (bit 0 for counter0, bit1 for counter1 and so on) > + and setting the corresponding bit will reserve that specific counter > + for counting cycles and override the event<N> setting. > + > +What: /sys/bus/platform/devices/<HID>/hwmon/hwmonX/<block>/use_odd_counter > +Date: May 2024 > +KernelVersion: 6.10 6.10 ship has already sailed. > +Contact: "Shravan Kumar Ramani <shravankr@nvidia.com>" > +Description: > + Form 64-bit counter using 2 32-bit counters. This is used to combine > + 2 adjacent counters to form a single 64-bit counter. Each even counter > + is represented by a bit and setting the bit will join the corresponding > + even counter with the next (odd) counter. The full 64-bit value can be > + accessed using the same 2 counter<N> and counter<N+1> sysfs, with each > + of them holding the lower and upper 32 bits respectively. Okay, thanks for updating this, it's much clearer now what the intent of each file is. One thing that is still unclear whether both bits are expected to be set in count_clock when use_odd_counter is used to combine two counters?
> > + Form 64-bit counter using 2 32-bit counters. This is used to combine > > + 2 adjacent counters to form a single 64-bit counter. Each even counter > > + is represented by a bit and setting the bit will join the corresponding > > + even counter with the next (odd) counter. The full 64-bit value can be > > + accessed using the same 2 counter<N> and counter<N+1> sysfs, with each > > + of them holding the lower and upper 32 bits respectively. > > Okay, thanks for updating this, it's much clearer now what the intent of > each file is. One thing that is still unclear whether both bits are > expected to be set in count_clock when use_odd_counter is used to combine > two counters? When use_odd_counter is set to combine counter0 and counter1, for example, the counter value will increment only based on what event is being monitored by counter0. So for counting cycles with 64-bits, count_clock needs to be set for counter0. Bit1 in count_clock as well as event1 will not matter once counter1 is joined to counter0. I will capture this as well in the doc in the next patch when I fix the kernel version. Thanks, Shravan
diff --git a/Documentation/ABI/testing/sysfs-platform-mellanox-pmc b/Documentation/ABI/testing/sysfs-platform-mellanox-pmc index 9f987c6410da..ee03d066c0d9 100644 --- a/Documentation/ABI/testing/sysfs-platform-mellanox-pmc +++ b/Documentation/ABI/testing/sysfs-platform-mellanox-pmc @@ -52,3 +52,26 @@ Description: Writing 0 to the sysfs will clear the counter, writing any other value is not allowed. +What: /sys/bus/platform/devices/<HID>/hwmon/hwmonX/<block>/count_clock +Date: May 2024 +KernelVersion: 6.10 +Contact: "Shravan Kumar Ramani <shravankr@nvidia.com>" +Description: + Use a counter for counting cycles. This is used to repurpose/dedicate + any of the counters in the block to counting cycles. Each counter is + represented by a bit (bit 0 for counter0, bit1 for counter1 and so on) + and setting the corresponding bit will reserve that specific counter + for counting cycles and override the event<N> setting. + +What: /sys/bus/platform/devices/<HID>/hwmon/hwmonX/<block>/use_odd_counter +Date: May 2024 +KernelVersion: 6.10 +Contact: "Shravan Kumar Ramani <shravankr@nvidia.com>" +Description: + Form 64-bit counter using 2 32-bit counters. This is used to combine + 2 adjacent counters to form a single 64-bit counter. Each even counter + is represented by a bit and setting the bit will join the corresponding + even counter with the next (odd) counter. The full 64-bit value can be + accessed using the same 2 counter<N> and counter<N+1> sysfs, with each + of them holding the lower and upper 32 bits respectively. +