| Message ID | 20240615170417.3134517-3-jonas@kwiboo.se (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | rockchip: Enable 4K@60Hz mode on RK3228, RK3328, RK3399 and RK356x | expand |
Am Samstag, 15. Juni 2024, 19:03:53 CEST schrieb Jonas Karlman: > Similar to DCLK_LCDC on RK3328, the DCLK_VOP on RK3228 is typically > parented by the hdmiphy clk and it is expected that the DCLK_VOP and > hdmiphy clk rate are kept in sync. > > Use CLK_SET_RATE_PARENT and CLK_SET_RATE_NO_REPARENT flags, same as used > on RK3328, to make full use of all possible supported display modes. > > Fixes: 0a9d4ac08ebc ("clk: rockchip: set the clock ids for RK3228 VOP") > Fixes: 307a2e9ac524 ("clk: rockchip: add clock controller for rk3228") > Signed-off-by: Jonas Karlman <jonas@kwiboo.se> did your mailer have a hickup? Somehow I got patch2 (only this one) 2 times
Hi Heiko, On 2024-06-17 22:30, Heiko Stübner wrote: > Am Samstag, 15. Juni 2024, 19:03:53 CEST schrieb Jonas Karlman: >> Similar to DCLK_LCDC on RK3328, the DCLK_VOP on RK3228 is typically >> parented by the hdmiphy clk and it is expected that the DCLK_VOP and >> hdmiphy clk rate are kept in sync. >> >> Use CLK_SET_RATE_PARENT and CLK_SET_RATE_NO_REPARENT flags, same as used >> on RK3328, to make full use of all possible supported display modes. >> >> Fixes: 0a9d4ac08ebc ("clk: rockchip: set the clock ids for RK3228 VOP") >> Fixes: 307a2e9ac524 ("clk: rockchip: add clock controller for rk3228") >> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> > > did your mailer have a hickup? Somehow I got patch2 (only this one) > 2 times > Strange, not something I know about, each patch 1-13 are listed as 250 Accepted (heiko@sntech.de) and patches arrived to the ML and patchwork: https://lore.kernel.org/all/20240615170417.3134517-1-jonas@kwiboo.se/ https://patchwork.freedesktop.org/series/134926/ https://patchwork.kernel.org/cover/13699322/ Regards, Jonas
On 2024-06-17 22:50, Jonas Karlman wrote: > On 2024-06-17 22:30, Heiko Stübner wrote: >> Am Samstag, 15. Juni 2024, 19:03:53 CEST schrieb Jonas Karlman: >>> Similar to DCLK_LCDC on RK3328, the DCLK_VOP on RK3228 is typically >>> parented by the hdmiphy clk and it is expected that the DCLK_VOP and >>> hdmiphy clk rate are kept in sync. >>> >>> Use CLK_SET_RATE_PARENT and CLK_SET_RATE_NO_REPARENT flags, same as >>> used >>> on RK3328, to make full use of all possible supported display modes. >>> >>> Fixes: 0a9d4ac08ebc ("clk: rockchip: set the clock ids for RK3228 >>> VOP") >>> Fixes: 307a2e9ac524 ("clk: rockchip: add clock controller for >>> rk3228") >>> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> >> >> did your mailer have a hickup? Somehow I got patch2 (only this one) >> 2 times > > Strange, not something I know about, each patch 1-13 are listed as 250 > Accepted (heiko@sntech.de) and patches arrived to the ML and patchwork: > > https://lore.kernel.org/all/20240615170417.3134517-1-jonas@kwiboo.se/ > https://patchwork.freedesktop.org/series/134926/ > https://patchwork.kernel.org/cover/13699322/ It might be that something is wrong with the MX host for sntech.de, I got one email rejected today with "invalid certificate" (or something like that) as the error message.
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c index a24a35553e13..7343d2d7676b 100644 --- a/drivers/clk/rockchip/clk-rk3228.c +++ b/drivers/clk/rockchip/clk-rk3228.c @@ -409,7 +409,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { RK2928_CLKSEL_CON(29), 0, 3, DFLAGS), DIV(0, "sclk_vop_pre", "sclk_vop_src", 0, RK2928_CLKSEL_CON(27), 8, 8, DFLAGS), - MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, 0, + MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, RK2928_CLKSEL_CON(27), 1, 1, MFLAGS), FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
Similar to DCLK_LCDC on RK3328, the DCLK_VOP on RK3228 is typically parented by the hdmiphy clk and it is expected that the DCLK_VOP and hdmiphy clk rate are kept in sync. Use CLK_SET_RATE_PARENT and CLK_SET_RATE_NO_REPARENT flags, same as used on RK3328, to make full use of all possible supported display modes. Fixes: 0a9d4ac08ebc ("clk: rockchip: set the clock ids for RK3228 VOP") Fixes: 307a2e9ac524 ("clk: rockchip: add clock controller for rk3228") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> --- drivers/clk/rockchip/clk-rk3228.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)