[RFC,v2,3/3] mmc: renesas_sdhi: Add support for RZ/V2H(P) SoC

Message ID	20240613091721.525266-4-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
State	Superseded
Delegated to:	Geert Uytterhoeven
Headers	show Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE8B913FD62; Thu, 13 Jun 2024 09:17:37 +0000 (UTC) From: Prabhakar <prabhakar.csengg@gmail.com> To: Wolfram Sang <wsa+renesas@sang-engineering.com>, Geert Uytterhoeven <geert+renesas@glider.be>, Ulf Hansson <ulf.hansson@linaro.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, Magnus Damm <magnus.damm@gmail.com> Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar <prabhakar.csengg@gmail.com>, Biju Das <biju.das.jz@bp.renesas.com>, Fabrizio Castro <fabrizio.castro.jz@renesas.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Subject: [RFC PATCH v2 3/3] mmc: renesas_sdhi: Add support for RZ/V2H(P) SoC Date: Thu, 13 Jun 2024 10:17:21 +0100 Message-Id: <20240613091721.525266-4-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20240613091721.525266-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240613091721.525266-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	Add SD/MMC support for Renesas RZ/V2H(P) SoC \| expand [RFC,v2,0/3] Add SD/MMC support for Renesas RZ/V2H(P) SoC [RFC,v2,1/3] dt-bindings: mmc: renesas,sdhi: Document RZ/V2H(P) support [RFC,v2,2/3] mmc: tmio: Use MMC core APIs to control the vqmmc regulator [RFC,v2,3/3] mmc: renesas_sdhi: Add support for RZ/V2H(P) SoC

diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdhi.h index 586f94d4dbfd..91e42e680dbb 100644 --- a/drivers/mmc/host/renesas_sdhi.h +++ b/drivers/mmc/host/renesas_sdhi.h @@ -11,6 +11,9 @@ #include <linux/dmaengine.h> #include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/regulator/driver.h> +#include <linux/regulator/machine.h> #include "tmio_mmc.h" struct renesas_sdhi_scc { @@ -49,6 +52,9 @@ struct renesas_sdhi_quirks { bool manual_tap_correction; bool old_info1_layout; u32 hs400_bad_taps; + bool internal_regulator; + struct regulator_desc *rdesc; + struct regulator_init_data *reg_init_data; const u8 (*hs400_calib_table)[SDHI_CALIB_TABLE_MAX]; }; @@ -93,6 +99,8 @@ struct renesas_sdhi { unsigned int tap_set; struct reset_control *rstc; + + struct regulator_dev *sd_status; }; #define host_to_priv(host) \ diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c index 12f4faaaf4ee..47e99ce0b752 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -587,6 +587,20 @@ static void renesas_sdhi_reset(struct tmio_mmc_host *host, bool preserve) false, priv->rstc); /* At least SDHI_VER_GEN2_SDR50 needs manual release of reset */ sd_ctrl_write16(host, CTL_RESET_SD, 0x0001); + if (sdhi_has_quirk(priv, internal_regulator)) { + unsigned int voltage; + + if (!regulator_is_enabled(host->mmc->supply.vqmmc)) + if (regulator_enable(host->mmc->supply.vqmmc)) + dev_err(&host->pdev->dev, "Failed to enable internal regulator\n"); + + /* restore back voltage on vqmmc supply */ + voltage = host->mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330 ? + 3300000 : 1800000; + regulator_set_voltage(host->mmc->supply.vqmmc, + voltage, voltage); + } + priv->needs_adjust_hs400 = false; renesas_sdhi_set_clock(host, host->clk_cache); @@ -904,6 +918,29 @@ static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable) renesas_sdhi_sdbuf_width(host, enable ? width : 16); } +static int renesas_sdhi_internal_dmac_register_regulator(struct platform_device *pdev, + const struct renesas_sdhi_quirks *quirks) +{ + struct tmio_mmc_host *host = platform_get_drvdata(pdev); + struct renesas_sdhi *priv = host_to_priv(host); + struct regulator_config rcfg = { + .dev = &pdev->dev, + .driver_data = host, + .init_data = quirks->reg_init_data, + }; + const char *devname; + + devname = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s-vqmmc-regulator", + dev_name(&pdev->dev)); + if (!devname) + return -ENOMEM; + + quirks->rdesc->name = devname; + priv->sd_status = devm_regulator_register(&pdev->dev, quirks->rdesc, &rcfg); + + return PTR_ERR_OR_ZERO(priv->sd_status); +} + int renesas_sdhi_probe(struct platform_device *pdev, const struct tmio_mmc_dma_ops *dma_ops, const struct renesas_sdhi_of_data *of_data, @@ -1051,6 +1088,12 @@ int renesas_sdhi_probe(struct platform_device *pdev, if (ret) goto efree; + if (sdhi_has_quirk(priv, internal_regulator)) { + ret = renesas_sdhi_internal_dmac_register_regulator(pdev, quirks); + if (ret) + goto efree; + } + ver = sd_ctrl_read16(host, CTL_VERSION); /* GEN2_SDR104 is first known SDHI to use 32bit block count */ if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX) diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c index 422fa63a2e99..ee0aafae9661 100644 --- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c +++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c @@ -215,6 +215,120 @@ static const struct renesas_sdhi_quirks sdhi_quirks_rzg2l = { .hs400_disabled = true, }; +static const unsigned int r9a09g057_vqmmc_voltages[] = { + 1800000, 3300000, +}; + +static int r9a09g057_regulator_disable(struct regulator_dev *rdev) +{ + struct tmio_mmc_host *host = rdev_get_drvdata(rdev); + u32 sd_status; + + sd_ctrl_read32_rep(host, CTL_SD_STATUS, &sd_status, 1); + sd_status &= ~SD_STATUS_PWEN; + sd_ctrl_write32(host, CTL_SD_STATUS, sd_status); + + return 0; +} + +static int r9a09g057_regulator_enable(struct regulator_dev *rdev) +{ + struct tmio_mmc_host *host = rdev_get_drvdata(rdev); + u32 sd_status; + + sd_ctrl_read32_rep(host, CTL_SD_STATUS, &sd_status, 1); + sd_status |= SD_STATUS_PWEN; + sd_ctrl_write32(host, CTL_SD_STATUS, sd_status); + + return 0; +} + +static int r9a09g057_regulator_is_enabled(struct regulator_dev *rdev) +{ + struct tmio_mmc_host *host = rdev_get_drvdata(rdev); + u32 sd_status; + + sd_ctrl_read32_rep(host, CTL_SD_STATUS, &sd_status, 1); + if (sd_status & SD_STATUS_PWEN) + return 1; + + return 0; +} + +static int r9a09g057_regulator_get_voltage(struct regulator_dev *rdev) +{ + struct tmio_mmc_host *host = rdev_get_drvdata(rdev); + u32 sd_status; + + sd_ctrl_read32_rep(host, CTL_SD_STATUS, &sd_status, 1); + if (sd_status & SD_STATUS_IOVS) + return 1800000; + + return 3300000; +} + +static int r9a09g057_regulator_set_voltage(struct regulator_dev *rdev, + int min_uV, int max_uV, + unsigned int *selector) +{ + struct tmio_mmc_host *host = rdev_get_drvdata(rdev); + u32 sd_status; + + sd_ctrl_read32_rep(host, CTL_SD_STATUS, &sd_status, 1); + if (min_uV >= 1700000 && max_uV <= 1950000) { + sd_status |= SD_STATUS_IOVS; + *selector = 0; + } else { + sd_status &= ~SD_STATUS_IOVS; + *selector = 1; + } + sd_ctrl_write32(host, CTL_SD_STATUS, sd_status); + + return 0; +} + +static int r9a09g057_regulator_list_voltage(struct regulator_dev *rdev, + unsigned selector) +{ + if (selector >= ARRAY_SIZE(r9a09g057_vqmmc_voltages)) + return -EINVAL; + + return r9a09g057_vqmmc_voltages[selector]; +} + +static struct regulator_init_data r9a09g057_regulator_init_data = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, +}; + +static const struct regulator_ops r9a09g057_regulator_voltage_ops = { + .enable = r9a09g057_regulator_enable, + .disable = r9a09g057_regulator_disable, + .is_enabled = r9a09g057_regulator_is_enabled, + .list_voltage = r9a09g057_regulator_list_voltage, + .get_voltage = r9a09g057_regulator_get_voltage, + .set_voltage = r9a09g057_regulator_set_voltage, + .map_voltage = regulator_map_voltage_ascend, +}; + +static struct regulator_desc r9a09g057_vqmmc_regulator = { + .of_match = of_match_ptr("vqmmc-r9a09g057-regulator"), + .owner = THIS_MODULE, + .type = REGULATOR_VOLTAGE, + .ops = &r9a09g057_regulator_voltage_ops, + .volt_table = r9a09g057_vqmmc_voltages, + .n_voltages = ARRAY_SIZE(r9a09g057_vqmmc_voltages), +}; + +static const struct renesas_sdhi_quirks sdhi_quirks_r9a09g057 = { + .fixed_addr_mode = true, + .hs400_disabled = true, + .internal_regulator = true, + .rdesc = &r9a09g057_vqmmc_regulator, + .reg_init_data = &r9a09g057_regulator_init_data, +}; + /* * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now. * So, we want to treat them equally and only have a match for ES1.2 to enforce @@ -260,6 +374,11 @@ static const struct renesas_sdhi_of_data_with_quirks of_rzg2l_compatible = { .quirks = &sdhi_quirks_rzg2l, }; +static const struct renesas_sdhi_of_data_with_quirks of_r9a09g057_compatible = { + .of_data = &of_data_rcar_gen3, + .quirks = &sdhi_quirks_r9a09g057, +}; + static const struct renesas_sdhi_of_data_with_quirks of_rcar_gen3_compatible = { .of_data = &of_data_rcar_gen3, }; @@ -284,6 +403,7 @@ static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = { { .compatible = "renesas,sdhi-r8a77990", .data = &of_r8a77990_compatible, }, { .compatible = "renesas,sdhi-r8a77995", .data = &of_rcar_gen3_nohs400_compatible, }, { .compatible = "renesas,sdhi-r9a09g011", .data = &of_rzg2l_compatible, }, + { .compatible = "renesas,sdhi-r9a09g057", .data = &of_r9a09g057_compatible, }, { .compatible = "renesas,rzg2l-sdhi", .data = &of_rzg2l_compatible, }, { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, }, { .compatible = "renesas,rcar-gen4-sdhi", .data = &of_rcar_gen3_compatible, }, diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h index de56e6534aea..1a3172786662 100644 --- a/drivers/mmc/host/tmio_mmc.h +++ b/drivers/mmc/host/tmio_mmc.h @@ -43,6 +43,7 @@ #define CTL_RESET_SD 0xe0 #define CTL_VERSION 0xe2 #define CTL_SDIF_MODE 0xe6 /* only known on R-Car 2+ */ +#define CTL_SD_STATUS 0xf2 /* only known on RZ/G2L and RZ/V2H(P) */ /* Definitions for values the CTL_STOP_INTERNAL_ACTION register can take */ #define TMIO_STOP_STP BIT(0) @@ -102,6 +103,10 @@ /* Definitions for values the CTL_SDIF_MODE register can take */ #define SDIF_MODE_HS400 BIT(0) /* only known on R-Car 2+ */ +/* Definitions for values the CTL_SD_STATUS register can take */ +#define SD_STATUS_PWEN BIT(0) /* only known on RZ/V2H(P) */ +#define SD_STATUS_IOVS BIT(16) /* only known on RZ/V2H(P) */ + /* Define some IRQ masks */ /* This is the mask used at reset by the chip */ #define TMIO_MASK_ALL 0x837f031d

[RFC,v2,3/3] mmc: renesas_sdhi: Add support for RZ/V2H(P) SoC

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