| Message ID | 20240621114659.2958170-2-quic_gokulsri@quicinc.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | remoteproc: qcom: q6v5-wcss: Add support for secure pil | expand |
On 21/06/2024 13:46, Gokul Sriram Palanisamy wrote: > > -static int q6v5_wcss_init_clock(struct q6v5_wcss *wcss) > +static int ipq8074_init_clock(struct q6v5_wcss *wcss) > +{ > + int ret; > + > + wcss->prng_clk = devm_clk_get(wcss->dev, "prng"); Missing binding. Best regards, Krzysztof
On Fri, Jun 21, 2024 at 05:16:52PM GMT, Gokul Sriram Palanisamy wrote: > PRNG clock is needed by the secure PIL, support for the same > is added in subsequent patches. Which 'same'? What is 'secure PIL'? > > Signed-off-by: Nikhil Prakash V <quic_nprakash@quicinc.com> > Signed-off-by: Sricharan R <quic_srichara@quicinc.com> > Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com> > --- > drivers/remoteproc/qcom_q6v5_wcss.c | 65 +++++++++++++++++++++-------- > 1 file changed, 47 insertions(+), 18 deletions(-) > > diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c > index 94f68c919ee6..366b19cbd994 100644 > --- a/drivers/remoteproc/qcom_q6v5_wcss.c > +++ b/drivers/remoteproc/qcom_q6v5_wcss.c > @@ -91,19 +91,6 @@ enum { > WCSS_QCS404, > }; > > -struct wcss_data { > - const char *firmware_name; > - unsigned int crash_reason_smem; > - u32 version; > - bool aon_reset_required; > - bool wcss_q6_reset_required; > - const char *ssr_name; > - const char *sysmon_name; > - int ssctl_id; > - const struct rproc_ops *ops; > - bool requires_force_stop; > -}; > - > struct q6v5_wcss { > struct device *dev; > > @@ -128,6 +115,7 @@ struct q6v5_wcss { > struct clk *qdsp6ss_xo_cbcr; > struct clk *qdsp6ss_core_gfmux; > struct clk *lcc_bcr_sleep; > + struct clk *prng_clk; > struct regulator *cx_supply; > struct qcom_sysmon *sysmon; > > @@ -151,6 +139,21 @@ struct q6v5_wcss { > struct qcom_rproc_ssr ssr_subdev; > }; > > +struct wcss_data { > + int (*init_clock)(struct q6v5_wcss *wcss); > + int (*init_regulator)(struct q6v5_wcss *wcss); > + const char *firmware_name; > + unsigned int crash_reason_smem; > + u32 version; > + bool aon_reset_required; > + bool wcss_q6_reset_required; > + const char *ssr_name; > + const char *sysmon_name; > + int ssctl_id; > + const struct rproc_ops *ops; > + bool requires_force_stop; > +}; Move this back and use forward-declaration of struct q6v5_wcss. > + > static int q6v5_wcss_reset(struct q6v5_wcss *wcss) > { > int ret;
On 6/21/2024 8:39 PM, Krzysztof Kozlowski wrote: > On 21/06/2024 13:46, Gokul Sriram Palanisamy wrote: >> >> -static int q6v5_wcss_init_clock(struct q6v5_wcss *wcss) >> +static int ipq8074_init_clock(struct q6v5_wcss *wcss) >> +{ >> + int ret; >> + >> + wcss->prng_clk = devm_clk_get(wcss->dev, "prng"); > Missing binding. Thanks. Will address and post this in new series. > Best regards, > Krzysztof >
On 6/22/2024 2:38 AM, Dmitry Baryshkov wrote: > On Fri, Jun 21, 2024 at 05:16:52PM GMT, Gokul Sriram Palanisamy wrote: >> PRNG clock is needed by the secure PIL, support for the same >> is added in subsequent patches. > Which 'same'? > What is 'secure PIL'? will elaborate in the updated version. To answer your question, secure PIL is signed PIL image which only TrustZone can authenticate and load. >> Signed-off-by: Nikhil Prakash V <quic_nprakash@quicinc.com> >> Signed-off-by: Sricharan R <quic_srichara@quicinc.com> >> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com> >> --- >> drivers/remoteproc/qcom_q6v5_wcss.c | 65 +++++++++++++++++++++-------- >> 1 file changed, 47 insertions(+), 18 deletions(-) >> >> diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c >> index 94f68c919ee6..366b19cbd994 100644 >> --- a/drivers/remoteproc/qcom_q6v5_wcss.c >> +++ b/drivers/remoteproc/qcom_q6v5_wcss.c >> @@ -91,19 +91,6 @@ enum { >> WCSS_QCS404, >> }; >> >> -struct wcss_data { >> - const char *firmware_name; >> - unsigned int crash_reason_smem; >> - u32 version; >> - bool aon_reset_required; >> - bool wcss_q6_reset_required; >> - const char *ssr_name; >> - const char *sysmon_name; >> - int ssctl_id; >> - const struct rproc_ops *ops; >> - bool requires_force_stop; >> -}; >> - >> struct q6v5_wcss { >> struct device *dev; >> >> @@ -128,6 +115,7 @@ struct q6v5_wcss { >> struct clk *qdsp6ss_xo_cbcr; >> struct clk *qdsp6ss_core_gfmux; >> struct clk *lcc_bcr_sleep; >> + struct clk *prng_clk; >> struct regulator *cx_supply; >> struct qcom_sysmon *sysmon; >> >> @@ -151,6 +139,21 @@ struct q6v5_wcss { >> struct qcom_rproc_ssr ssr_subdev; >> }; >> >> +struct wcss_data { >> + int (*init_clock)(struct q6v5_wcss *wcss); >> + int (*init_regulator)(struct q6v5_wcss *wcss); >> + const char *firmware_name; >> + unsigned int crash_reason_smem; >> + u32 version; >> + bool aon_reset_required; >> + bool wcss_q6_reset_required; >> + const char *ssr_name; >> + const char *sysmon_name; >> + int ssctl_id; >> + const struct rproc_ops *ops; >> + bool requires_force_stop; >> +}; > Move this back and use forward-declaration of struct q6v5_wcss. sure. Will update. >> + >> static int q6v5_wcss_reset(struct q6v5_wcss *wcss) >> { >> int ret;
On Tue, Jun 25, 2024 at 11:03:30AM GMT, Gokul Sriram P wrote: > > On 6/22/2024 2:38 AM, Dmitry Baryshkov wrote: > > On Fri, Jun 21, 2024 at 05:16:52PM GMT, Gokul Sriram Palanisamy wrote: > > > PRNG clock is needed by the secure PIL, support for the same > > > is added in subsequent patches. > > Which 'same'? > > What is 'secure PIL'? > will elaborate in the updated version. > To answer your question, secure PIL is signed PIL image which only > TrustZone can authenticate and load. Fine. So, the current driver can not load WCSS firmware on IPQ8074, is that correct? Or was there some kind of firmware interface change? The driver was added in 2018, so I can only hope that at that point it worked. Could you please explain, what happened? > > > Signed-off-by: Nikhil Prakash V <quic_nprakash@quicinc.com> > > > Signed-off-by: Sricharan R <quic_srichara@quicinc.com> > > > Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com> > > > --- > > > drivers/remoteproc/qcom_q6v5_wcss.c | 65 +++++++++++++++++++++-------- > > > 1 file changed, 47 insertions(+), 18 deletions(-)
On 6/27/2024 12:47 AM, Dmitry Baryshkov wrote: > On Tue, Jun 25, 2024 at 11:03:30AM GMT, Gokul Sriram P wrote: >> On 6/22/2024 2:38 AM, Dmitry Baryshkov wrote: >>> On Fri, Jun 21, 2024 at 05:16:52PM GMT, Gokul Sriram Palanisamy wrote: >>>> PRNG clock is needed by the secure PIL, support for the same >>>> is added in subsequent patches. >>> Which 'same'? >>> What is 'secure PIL'? >> will elaborate in the updated version. >> To answer your question, secure PIL is signed PIL image which only >> TrustZone can authenticate and load. > Fine. So, the current driver can not load WCSS firmware on IPQ8074, is > that correct? Or was there some kind of firmware interface change? The > driver was added in 2018, so I can only hope that at that point it > worked. Could you please explain, what happened? The existing wcss driver can load unsigned PIL images without the involvement of TrustZone. That works even now. With the current change, we are trying to add signed PIL as an option based on "wcss->need_mem_protection" if set. For signed PIL alone, we send a PAS request to TrustZone to authenticate and load. I also just noticed that Bjorn had suggested to submit a new driver for the PAS based IPQ WCSS instead of overloading this driver. Will also address that and post a new driver in updated revision. Regards, Gokul >>>> Signed-off-by: Nikhil Prakash V <quic_nprakash@quicinc.com> >>>> Signed-off-by: Sricharan R <quic_srichara@quicinc.com> >>>> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com> >>>> --- >>>> drivers/remoteproc/qcom_q6v5_wcss.c | 65 +++++++++++++++++++++-------- >>>> 1 file changed, 47 insertions(+), 18 deletions(-) >
On Thu, Jun 27, 2024 at 03:31:01PM GMT, Gokul Sriram P wrote: > > On 6/27/2024 12:47 AM, Dmitry Baryshkov wrote: > > On Tue, Jun 25, 2024 at 11:03:30AM GMT, Gokul Sriram P wrote: > > > On 6/22/2024 2:38 AM, Dmitry Baryshkov wrote: > > > > On Fri, Jun 21, 2024 at 05:16:52PM GMT, Gokul Sriram Palanisamy wrote: > > > > > PRNG clock is needed by the secure PIL, support for the same > > > > > is added in subsequent patches. > > > > Which 'same'? > > > > What is 'secure PIL'? > > > will elaborate in the updated version. > > > To answer your question, secure PIL is signed PIL image which only > > > TrustZone can authenticate and load. > > Fine. So, the current driver can not load WCSS firmware on IPQ8074, is > > that correct? Or was there some kind of firmware interface change? The > > driver was added in 2018, so I can only hope that at that point it > > worked. Could you please explain, what happened? > The existing wcss driver can load unsigned PIL images without the > involvement of TrustZone. That works even now. > With the current change, we are trying to add signed PIL as an option based > on "wcss->need_mem_protection" if set. For signed PIL alone, we send a PAS > request to TrustZone to authenticate and load. I see that you are enabling it unconditionally for IPQ8074. How is it going to work? > I also just noticed that Bjorn had suggested to submit a new driver for the > PAS based IPQ WCSS instead of overloading this driver. Will also address > that and post a new driver in updated revision. > > Regards, > Gokul > > > > > Signed-off-by: Nikhil Prakash V <quic_nprakash@quicinc.com> > > > > > Signed-off-by: Sricharan R <quic_srichara@quicinc.com> > > > > > Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com> > > > > > --- > > > > > drivers/remoteproc/qcom_q6v5_wcss.c | 65 +++++++++++++++++++++-------- > > > > > 1 file changed, 47 insertions(+), 18 deletions(-) > >
On 6/27/2024 4:38 PM, Dmitry Baryshkov wrote: > On Thu, Jun 27, 2024 at 03:31:01PM GMT, Gokul Sriram P wrote: >> On 6/27/2024 12:47 AM, Dmitry Baryshkov wrote: >>> On Tue, Jun 25, 2024 at 11:03:30AM GMT, Gokul Sriram P wrote: >>>> On 6/22/2024 2:38 AM, Dmitry Baryshkov wrote: >>>>> On Fri, Jun 21, 2024 at 05:16:52PM GMT, Gokul Sriram Palanisamy wrote: >>>>>> PRNG clock is needed by the secure PIL, support for the same >>>>>> is added in subsequent patches. >>>>> Which 'same'? >>>>> What is 'secure PIL'? >>>> will elaborate in the updated version. >>>> To answer your question, secure PIL is signed PIL image which only >>>> TrustZone can authenticate and load. >>> Fine. So, the current driver can not load WCSS firmware on IPQ8074, is >>> that correct? Or was there some kind of firmware interface change? The >>> driver was added in 2018, so I can only hope that at that point it >>> worked. Could you please explain, what happened? >> The existing wcss driver can load unsigned PIL images without the >> involvement of TrustZone. That works even now. >> With the current change, we are trying to add signed PIL as an option based >> on "wcss->need_mem_protection" if set. For signed PIL alone, we send a PAS >> request to TrustZone to authenticate and load. > I see that you are enabling it unconditionally for IPQ8074. How is it > going to work? Correct Dmitry. In this change, it is forcing secure PIL. With a separate driver for secure PIL, this will be sorted right? Regards, Gokul >> I also just noticed that Bjorn had suggested to submit a new driver for the >> PAS based IPQ WCSS instead of overloading this driver. Will also address >> that and post a new driver in updated revision. >> >> Regards, >> Gokul >>>>>> Signed-off-by: Nikhil Prakash V <quic_nprakash@quicinc.com> >>>>>> Signed-off-by: Sricharan R <quic_srichara@quicinc.com> >>>>>> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com> >>>>>> --- >>>>>> drivers/remoteproc/qcom_q6v5_wcss.c | 65 +++++++++++++++++++++-------- >>>>>> 1 file changed, 47 insertions(+), 18 deletions(-)
On Thu, Jun 27, 2024 at 04:59:38PM GMT, Gokul Sriram P wrote: > > On 6/27/2024 4:38 PM, Dmitry Baryshkov wrote: > > On Thu, Jun 27, 2024 at 03:31:01PM GMT, Gokul Sriram P wrote: > > > On 6/27/2024 12:47 AM, Dmitry Baryshkov wrote: > > > > On Tue, Jun 25, 2024 at 11:03:30AM GMT, Gokul Sriram P wrote: > > > > > On 6/22/2024 2:38 AM, Dmitry Baryshkov wrote: > > > > > > On Fri, Jun 21, 2024 at 05:16:52PM GMT, Gokul Sriram Palanisamy wrote: > > > > > > > PRNG clock is needed by the secure PIL, support for the same > > > > > > > is added in subsequent patches. > > > > > > Which 'same'? > > > > > > What is 'secure PIL'? > > > > > will elaborate in the updated version. > > > > > To answer your question, secure PIL is signed PIL image which only > > > > > TrustZone can authenticate and load. > > > > Fine. So, the current driver can not load WCSS firmware on IPQ8074, is > > > > that correct? Or was there some kind of firmware interface change? The > > > > driver was added in 2018, so I can only hope that at that point it > > > > worked. Could you please explain, what happened? > > > The existing wcss driver can load unsigned PIL images without the > > > involvement of TrustZone. That works even now. > > > With the current change, we are trying to add signed PIL as an option based > > > on "wcss->need_mem_protection" if set. For signed PIL alone, we send a PAS > > > request to TrustZone to authenticate and load. > > I see that you are enabling it unconditionally for IPQ8074. How is it > > going to work? > > Correct Dmitry. In this change, it is forcing secure PIL. With a separate > driver for secure PIL, this will be sorted right? That depends. How will the running system decide, which driver to use? It can not be a compile-time decision. > > Regards, > > Gokul > > > > I also just noticed that Bjorn had suggested to submit a new driver for the > > > PAS based IPQ WCSS instead of overloading this driver. Will also address > > > that and post a new driver in updated revision. > > > > > > Regards, > > > Gokul > > > > > > > Signed-off-by: Nikhil Prakash V <quic_nprakash@quicinc.com> > > > > > > > Signed-off-by: Sricharan R <quic_srichara@quicinc.com> > > > > > > > Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com> > > > > > > > --- > > > > > > > drivers/remoteproc/qcom_q6v5_wcss.c | 65 +++++++++++++++++++++-------- > > > > > > > 1 file changed, 47 insertions(+), 18 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c index 94f68c919ee6..366b19cbd994 100644 --- a/drivers/remoteproc/qcom_q6v5_wcss.c +++ b/drivers/remoteproc/qcom_q6v5_wcss.c @@ -91,19 +91,6 @@ enum { WCSS_QCS404, }; -struct wcss_data { - const char *firmware_name; - unsigned int crash_reason_smem; - u32 version; - bool aon_reset_required; - bool wcss_q6_reset_required; - const char *ssr_name; - const char *sysmon_name; - int ssctl_id; - const struct rproc_ops *ops; - bool requires_force_stop; -}; - struct q6v5_wcss { struct device *dev; @@ -128,6 +115,7 @@ struct q6v5_wcss { struct clk *qdsp6ss_xo_cbcr; struct clk *qdsp6ss_core_gfmux; struct clk *lcc_bcr_sleep; + struct clk *prng_clk; struct regulator *cx_supply; struct qcom_sysmon *sysmon; @@ -151,6 +139,21 @@ struct q6v5_wcss { struct qcom_rproc_ssr ssr_subdev; }; +struct wcss_data { + int (*init_clock)(struct q6v5_wcss *wcss); + int (*init_regulator)(struct q6v5_wcss *wcss); + const char *firmware_name; + unsigned int crash_reason_smem; + u32 version; + bool aon_reset_required; + bool wcss_q6_reset_required; + const char *ssr_name; + const char *sysmon_name; + int ssctl_id; + const struct rproc_ops *ops; + bool requires_force_stop; +}; + static int q6v5_wcss_reset(struct q6v5_wcss *wcss) { int ret; @@ -240,6 +243,12 @@ static int q6v5_wcss_start(struct rproc *rproc) struct q6v5_wcss *wcss = rproc->priv; int ret; + ret = clk_prepare_enable(wcss->prng_clk); + if (ret) { + dev_err(wcss->dev, "prng clock enable failed\n"); + return ret; + } + qcom_q6v5_prepare(&wcss->q6v5); /* Release Q6 and WCSS reset */ @@ -733,6 +742,7 @@ static int q6v5_wcss_stop(struct rproc *rproc) return ret; } + clk_disable_unprepare(wcss->prng_clk); qcom_q6v5_unprepare(&wcss->q6v5); return 0; @@ -899,7 +909,21 @@ static int q6v5_alloc_memory_region(struct q6v5_wcss *wcss) return 0; } -static int q6v5_wcss_init_clock(struct q6v5_wcss *wcss) +static int ipq8074_init_clock(struct q6v5_wcss *wcss) +{ + int ret; + + wcss->prng_clk = devm_clk_get(wcss->dev, "prng"); + if (IS_ERR(wcss->prng_clk)) { + ret = PTR_ERR(wcss->prng_clk); + if (ret != -EPROBE_DEFER) + dev_err(wcss->dev, "Failed to get prng clock\n"); + return ret; + } + return 0; +} + +static int qcs404_init_clock(struct q6v5_wcss *wcss) { int ret; @@ -989,7 +1013,7 @@ static int q6v5_wcss_init_clock(struct q6v5_wcss *wcss) return 0; } -static int q6v5_wcss_init_regulator(struct q6v5_wcss *wcss) +static int qcs404_init_regulator(struct q6v5_wcss *wcss) { wcss->cx_supply = devm_regulator_get(wcss->dev, "cx"); if (IS_ERR(wcss->cx_supply)) @@ -1033,12 +1057,14 @@ static int q6v5_wcss_probe(struct platform_device *pdev) if (ret) return ret; - if (wcss->version == WCSS_QCS404) { - ret = q6v5_wcss_init_clock(wcss); + if (desc->init_clock) { + ret = desc->init_clock(wcss); if (ret) return ret; + } - ret = q6v5_wcss_init_regulator(wcss); + if (desc->init_regulator) { + ret = desc->init_regulator(wcss); if (ret) return ret; } @@ -1078,6 +1104,7 @@ static void q6v5_wcss_remove(struct platform_device *pdev) } static const struct wcss_data wcss_ipq8074_res_init = { + .init_clock = ipq8074_init_clock, .firmware_name = "IPQ8074/q6_fw.mdt", .crash_reason_smem = WCSS_CRASH_REASON, .aon_reset_required = true, @@ -1087,6 +1114,8 @@ static const struct wcss_data wcss_ipq8074_res_init = { }; static const struct wcss_data wcss_qcs404_res_init = { + .init_clock = qcs404_init_clock, + .init_regulator = qcs404_init_regulator, .crash_reason_smem = WCSS_CRASH_REASON, .firmware_name = "wcnss.mdt", .version = WCSS_QCS404,