Message ID | 20240621114659.2958170-7-quic_gokulsri@quicinc.com (mailing list archive) |
---|---|
State | Awaiting Upstream, archived |
Headers | show |
Series | remoteproc: qcom: q6v5-wcss: Add support for secure pil | expand |
On 21/06/2024 13:46, Gokul Sriram Palanisamy wrote: > Add binding for WCSSAON reset required for Q6v5 reset on IPQ8074 SoC. > > Signed-off-by: Nikhil Prakash V <quic_nprakash@quicinc.com> > Signed-off-by: Sricharan R <quic_srichara@quicinc.com> > Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com> Again, three people contributed to this one define? Best regards, Krzysztof
On 6/21/2024 5:16 PM, Gokul Sriram Palanisamy wrote: > Add binding for WCSSAON reset required for Q6v5 reset on IPQ8074 SoC. Can we include ipq8074 in the title? "dt-bindings: clock: qcom: ipq8074: Add reset for WCSSAON" > > Signed-off-by: Nikhil Prakash V <quic_nprakash@quicinc.com> > Signed-off-by: Sricharan R <quic_srichara@quicinc.com> > Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com> > Acked-by: Rob Herring <robh@kernel.org> > Acked-by: Stephen Boyd <sboyd@kernel.org> > --- > include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h > index f9ea55811104..e47cbf7394aa 100644 > --- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h > +++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h > @@ -381,6 +381,7 @@ > #define GCC_NSSPORT4_RESET 143 > #define GCC_NSSPORT5_RESET 144 > #define GCC_NSSPORT6_RESET 145 > +#define GCC_WCSSAON_RESET 146 > > #define USB0_GDSC 0 > #define USB1_GDSC 1
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h index f9ea55811104..e47cbf7394aa 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h @@ -381,6 +381,7 @@ #define GCC_NSSPORT4_RESET 143 #define GCC_NSSPORT5_RESET 144 #define GCC_NSSPORT6_RESET 145 +#define GCC_WCSSAON_RESET 146 #define USB0_GDSC 0 #define USB1_GDSC 1