diff mbox series

drm/msm/dpu: guard ctl irq callback register/unregister

Message ID 20240509-ctl_irq-v1-1-9433f2da9dc7@gmail.com (mailing list archive)
State New, archived
Headers show
Series drm/msm/dpu: guard ctl irq callback register/unregister | expand

Commit Message

Barnabás Czémán May 9, 2024, 5:52 p.m. UTC
CTLs on older qualcomm SOCs like msm8953 and msm8996 has not got interrupts,
so better to skip CTL irq callback register/unregister
make dpu_ctl_cfg be able to define without intr_start.

Signed-off-by: Barnabás Czémán <trabarni@gmail.com>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)


---
base-commit: 704ba27ac55579704ba1289392448b0c66b56258
change-id: 20240509-ctl_irq-a90b2d7a0bf5

Best regards,

Comments

Abhinav Kumar May 9, 2024, 7:14 p.m. UTC | #1
On 5/9/2024 10:52 AM, Barnabás Czémán wrote:
> CTLs on older qualcomm SOCs like msm8953 and msm8996 has not got interrupts,
> so better to skip CTL irq callback register/unregister
> make dpu_ctl_cfg be able to define without intr_start.
> 

Thanks for the patch.

Have msm8953 and msm8996 migrated to DPU or is there a series planned to 
migrate them?

The change itself is correct but without the catalogs for those chipsets 
merged, we will never hit this path.


> Signed-off-by: Barnabás Czémán <trabarni@gmail.com>
> ---
>   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> index 489be1c0c704..250d83af53a4 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> @@ -298,7 +298,7 @@ static void dpu_encoder_phys_cmd_irq_enable(struct dpu_encoder_phys *phys_enc)
>   				       phys_enc);
>   	dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, true);
>   
> -	if (dpu_encoder_phys_cmd_is_master(phys_enc))
> +	if (dpu_encoder_phys_cmd_is_master(phys_enc) && phys_enc->irq[INTR_IDX_CTL_START])
>   		dpu_core_irq_register_callback(phys_enc->dpu_kms,
>   					       phys_enc->irq[INTR_IDX_CTL_START],
>   					       dpu_encoder_phys_cmd_ctl_start_irq,
> @@ -311,7 +311,7 @@ static void dpu_encoder_phys_cmd_irq_disable(struct dpu_encoder_phys *phys_enc)
>   					   phys_enc->hw_pp->idx - PINGPONG_0,
>   					   phys_enc->vblank_refcount);
>   
> -	if (dpu_encoder_phys_cmd_is_master(phys_enc))
> +	if (dpu_encoder_phys_cmd_is_master(phys_enc) && phys_enc->irq[INTR_IDX_CTL_START])
>   		dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
>   						 phys_enc->irq[INTR_IDX_CTL_START]);
>   
> 
> ---
> base-commit: 704ba27ac55579704ba1289392448b0c66b56258
> change-id: 20240509-ctl_irq-a90b2d7a0bf5
> 
> Best regards,
Barnabás Czémán May 9, 2024, 7:27 p.m. UTC | #2
There was some previously sent patch series made by Dmitry for these soc,
msm8996 was sent together by sdm660 but in the last version it was dropped.
I have recreated msm8996 DPU support from that series but it will need
some more test.
I am testing msm8953 series but it is depend on msm8996.
Dmitry Baryshkov June 22, 2024, 11:39 a.m. UTC | #3
On Thu, May 09, 2024 at 12:14:19PM GMT, Abhinav Kumar wrote:
> 
> 
> On 5/9/2024 10:52 AM, Barnabás Czémán wrote:
> > CTLs on older qualcomm SOCs like msm8953 and msm8996 has not got interrupts,
> > so better to skip CTL irq callback register/unregister
> > make dpu_ctl_cfg be able to define without intr_start.
> > 
> 
> Thanks for the patch.
> 
> Have msm8953 and msm8996 migrated to DPU or is there a series planned to
> migrate them?
> 
> The change itself is correct but without the catalogs for those chipsets
> merged, we will never hit this path.

I think I'm going to accept this patch. While we might not be supporting
these chipsets, it's easier to have this in.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

> > Signed-off-by: Barnabás Czémán <trabarni@gmail.com>
> > ---
> >   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 4 ++--
> >   1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> > index 489be1c0c704..250d83af53a4 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> > @@ -298,7 +298,7 @@ static void dpu_encoder_phys_cmd_irq_enable(struct dpu_encoder_phys *phys_enc)
> >   				       phys_enc);
> >   	dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, true);
> > -	if (dpu_encoder_phys_cmd_is_master(phys_enc))
> > +	if (dpu_encoder_phys_cmd_is_master(phys_enc) && phys_enc->irq[INTR_IDX_CTL_START])
> >   		dpu_core_irq_register_callback(phys_enc->dpu_kms,
> >   					       phys_enc->irq[INTR_IDX_CTL_START],
> >   					       dpu_encoder_phys_cmd_ctl_start_irq,
> > @@ -311,7 +311,7 @@ static void dpu_encoder_phys_cmd_irq_disable(struct dpu_encoder_phys *phys_enc)
> >   					   phys_enc->hw_pp->idx - PINGPONG_0,
> >   					   phys_enc->vblank_refcount);
> > -	if (dpu_encoder_phys_cmd_is_master(phys_enc))
> > +	if (dpu_encoder_phys_cmd_is_master(phys_enc) && phys_enc->irq[INTR_IDX_CTL_START])
> >   		dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
> >   						 phys_enc->irq[INTR_IDX_CTL_START]);
> > 
> > ---
> > base-commit: 704ba27ac55579704ba1289392448b0c66b56258
> > change-id: 20240509-ctl_irq-a90b2d7a0bf5
> > 
> > Best regards,
Dmitry Baryshkov June 23, 2024, 7:14 a.m. UTC | #4
On Thu, 09 May 2024 19:52:04 +0200, Barnabás Czémán wrote:
> CTLs on older qualcomm SOCs like msm8953 and msm8996 has not got interrupts,
> so better to skip CTL irq callback register/unregister
> make dpu_ctl_cfg be able to define without intr_start.
> 
> 

Applied, thanks!

[1/1] drm/msm/dpu: guard ctl irq callback register/unregister
      https://gitlab.freedesktop.org/lumag/msm/-/commit/29cd76c6f897

Best regards,
diff mbox series

Patch

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index 489be1c0c704..250d83af53a4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -298,7 +298,7 @@  static void dpu_encoder_phys_cmd_irq_enable(struct dpu_encoder_phys *phys_enc)
 				       phys_enc);
 	dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, true);
 
-	if (dpu_encoder_phys_cmd_is_master(phys_enc))
+	if (dpu_encoder_phys_cmd_is_master(phys_enc) && phys_enc->irq[INTR_IDX_CTL_START])
 		dpu_core_irq_register_callback(phys_enc->dpu_kms,
 					       phys_enc->irq[INTR_IDX_CTL_START],
 					       dpu_encoder_phys_cmd_ctl_start_irq,
@@ -311,7 +311,7 @@  static void dpu_encoder_phys_cmd_irq_disable(struct dpu_encoder_phys *phys_enc)
 					   phys_enc->hw_pp->idx - PINGPONG_0,
 					   phys_enc->vblank_refcount);
 
-	if (dpu_encoder_phys_cmd_is_master(phys_enc))
+	if (dpu_encoder_phys_cmd_is_master(phys_enc) && phys_enc->irq[INTR_IDX_CTL_START])
 		dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
 						 phys_enc->irq[INTR_IDX_CTL_START]);