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[v5,00/13] PCI: dw-rockchip: Add endpoint mode support

Message ID 20240607-rockchip-pcie-ep-v1-v5-0-0a042d6b0049@kernel.org (mailing list archive)
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Series PCI: dw-rockchip: Add endpoint mode support | expand

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Niklas Cassel June 7, 2024, 11:14 a.m. UTC
Hello all,

This series adds PCIe endpoint mode support for the rockchip rk3588 and
rk3568 SoCs.

This series is based on: pci/next
(git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git)

This series can also be found in git:
https://github.com/floatious/linux/commits/rockchip-pcie-ep-v5

Testing done:
This series has been tested with two rock5b:s, one running in RC mode and
one running in EP mode. This series has also been tested with an Intel x86
host and rock5b running in EP mode.

BAR4 exposes the ATU Port Logic Structure and the DMA Port Logic Structure
to the host. The EPC controller driver thus disables this BAR as init time,
because if it doesn't, when the host writes the test pattern to this BAR,
all the iATU settings will get wiped, resulting in all further BAR accesses
being non-functional.

Running pcitest.sh (modified to also perform the READ and WRITE tests with
the -d option, i.e. with DMA enabled) results in the following:

$ /usr/bin/pcitest.sh
BAR tests

BAR0:           OKAY
BAR1:           OKAY
BAR2:           OKAY
BAR3:           OKAY
BAR4:           NOT OKAY
BAR5:           OKAY

Interrupt tests

SET IRQ TYPE TO LEGACY:         OKAY
LEGACY IRQ:     NOT OKAY
SET IRQ TYPE TO MSI:            OKAY
MSI1:           OKAY
MSI2:           OKAY
MSI3:           OKAY
MSI4:           OKAY
MSI5:           OKAY
MSI6:           OKAY
MSI7:           OKAY
MSI8:           OKAY
MSI9:           OKAY
MSI10:          OKAY
MSI11:          OKAY
MSI12:          OKAY
MSI13:          OKAY
MSI14:          OKAY
MSI15:          OKAY
MSI16:          OKAY
MSI17:          OKAY
MSI18:          OKAY
MSI19:          OKAY
MSI20:          OKAY
MSI21:          OKAY
MSI22:          OKAY
MSI23:          OKAY
MSI24:          OKAY
MSI25:          OKAY
MSI26:          OKAY
MSI27:          OKAY
MSI28:          OKAY
MSI29:          OKAY
MSI30:          OKAY
MSI31:          OKAY
MSI32:          OKAY

SET IRQ TYPE TO MSI-X:          OKAY
MSI-X1:         OKAY
MSI-X2:         OKAY
MSI-X3:         OKAY
MSI-X4:         OKAY
MSI-X5:         OKAY
MSI-X6:         OKAY
MSI-X7:         OKAY
MSI-X8:         OKAY
MSI-X9:         OKAY
MSI-X10:                OKAY
MSI-X11:                OKAY
MSI-X12:                OKAY
MSI-X13:                OKAY
MSI-X14:                OKAY
MSI-X15:                OKAY
MSI-X16:                OKAY
MSI-X17:                OKAY
MSI-X18:                OKAY
MSI-X19:                OKAY
MSI-X20:                OKAY
MSI-X21:                OKAY
MSI-X22:                OKAY
MSI-X23:                OKAY
MSI-X24:                OKAY
MSI-X25:                OKAY
MSI-X26:                OKAY
MSI-X27:                OKAY
MSI-X28:                OKAY
MSI-X29:                OKAY
MSI-X30:                OKAY
MSI-X31:                OKAY
MSI-X32:                OKAY

Read Tests

SET IRQ TYPE TO MSI:            OKAY
READ (      1 bytes):           OKAY
READ (   1024 bytes):           OKAY
READ (   1025 bytes):           OKAY
READ (1024000 bytes):           OKAY
READ (1024001 bytes):           OKAY

Write Tests

WRITE (      1 bytes):          OKAY
WRITE (   1024 bytes):          OKAY
WRITE (   1025 bytes):          OKAY
WRITE (1024000 bytes):          OKAY
WRITE (1024001 bytes):          OKAY

Copy Tests

COPY (      1 bytes):           OKAY
COPY (   1024 bytes):           OKAY
COPY (   1025 bytes):           OKAY
COPY (1024000 bytes):           OKAY
COPY (1024001 bytes):           OKAY

Read Tests DMA

READ (      1 bytes):           OKAY
READ (   1024 bytes):           OKAY
READ (   1025 bytes):           OKAY
READ (1024000 bytes):           OKAY
READ (1024001 bytes):           OKAY

Write Tests DMA

WRITE (      1 bytes):          OKAY
WRITE (   1024 bytes):          OKAY
WRITE (   1025 bytes):          OKAY
WRITE (1024000 bytes):          OKAY
WRITE (1024001 bytes):          OKAY

Corresponding output on the EP side:
rockchip-dw-pcie a40000000.pcie-ep: EP cannot raise INTX IRQs
pci_epf_test pci_epf_test.0: WRITE => Size: 1 B, DMA: NO, Time: 0.000000292 s, Rate: 3424 KB/s
pci_epf_test pci_epf_test.0: WRITE => Size: 1024 B, DMA: NO, Time: 0.000007583 s, Rate: 135038 KB/s
pci_epf_test pci_epf_test.0: WRITE => Size: 1025 B, DMA: NO, Time: 0.000007584 s, Rate: 135152 KB/s
pci_epf_test pci_epf_test.0: WRITE => Size: 1024000 B, DMA: NO, Time: 0.009164167 s, Rate: 111739 KB/s
pci_epf_test pci_epf_test.0: WRITE => Size: 1024001 B, DMA: NO, Time: 0.009164458 s, Rate: 111736 KB/s
pci_epf_test pci_epf_test.0: READ => Size: 1 B, DMA: NO, Time: 0.000001750 s, Rate: 571 KB/s
pci_epf_test pci_epf_test.0: READ => Size: 1024 B, DMA: NO, Time: 0.000147875 s, Rate: 6924 KB/s
pci_epf_test pci_epf_test.0: READ => Size: 1025 B, DMA: NO, Time: 0.000149041 s, Rate: 6877 KB/s
pci_epf_test pci_epf_test.0: READ => Size: 1024000 B, DMA: NO, Time: 0.147537833 s, Rate: 6940 KB/s
pci_epf_test pci_epf_test.0: READ => Size: 1024001 B, DMA: NO, Time: 0.147533750 s, Rate: 6940 KB/s
pci_epf_test pci_epf_test.0: COPY => Size: 1 B, DMA: NO, Time: 0.000003208 s, Rate: 311 KB/s
pci_epf_test pci_epf_test.0: COPY => Size: 1024 B, DMA: NO, Time: 0.000156625 s, Rate: 6537 KB/s
pci_epf_test pci_epf_test.0: COPY => Size: 1025 B, DMA: NO, Time: 0.000158375 s, Rate: 6471 KB/s
pci_epf_test pci_epf_test.0: COPY => Size: 1024000 B, DMA: NO, Time: 0.156902666 s, Rate: 6526 KB/s
pci_epf_test pci_epf_test.0: COPY => Size: 1024001 B, DMA: NO, Time: 0.156847833 s, Rate: 6528 KB/s
pci_epf_test pci_epf_test.0: WRITE => Size: 1 B, DMA: YES, Time: 0.000185500 s, Rate: 5 KB/s
pci_epf_test pci_epf_test.0: WRITE => Size: 1024 B, DMA: YES, Time: 0.000177334 s, Rate: 5774 KB/s
pci_epf_test pci_epf_test.0: WRITE => Size: 1025 B, DMA: YES, Time: 0.000178792 s, Rate: 5732 KB/s
pci_epf_test pci_epf_test.0: WRITE => Size: 1024000 B, DMA: YES, Time: 0.000486209 s, Rate: 2106090 KB/s
pci_epf_test pci_epf_test.0: WRITE => Size: 1024001 B, DMA: YES, Time: 0.000486791 s, Rate: 2103574 KB/s
pci_epf_test pci_epf_test.0: READ => Size: 1 B, DMA: YES, Time: 0.000177333 s, Rate: 5 KB/s
pci_epf_test pci_epf_test.0: READ => Size: 1024 B, DMA: YES, Time: 0.000177625 s, Rate: 5764 KB/s
pci_epf_test pci_epf_test.0: READ => Size: 1025 B, DMA: YES, Time: 0.000171208 s, Rate: 5986 KB/s
pci_epf_test pci_epf_test.0: READ => Size: 1024000 B, DMA: YES, Time: 0.000701167 s, Rate: 1460422 KB/s
pci_epf_test pci_epf_test.0: READ => Size: 1024001 B, DMA: YES, Time: 0.000702625 s, Rate: 1457393 KB/s

Kind regards,
Niklas

---
Changes in v5:
- Picked up tags from Mani, thank you!
- Fixed minor nits in DT binding patch.
- Improved indentation in refactor patch.
- Reordered reg and reg-names after compatible.
- Fix Makefile to build driver if PCIE_ROCKCHIP_DW instead of
  PCIE_ROCKCHIP_DW_HOST (this was a bug).
- Clear the interrupt directly after reading the status, instead
  of at the end of the irq handler.
- Link to v4: https://lore.kernel.org/r/20240529-rockchip-pcie-ep-v1-v4-0-3dc00fe21a78@kernel.org

Changes in v4:
- Rebased on pci/next
- Link to v3: https://lore.kernel.org/r/20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org

Changes in v3:
- Renamed rockchip_pcie_ltssm() to rockchip_pcie_get_ltssm()
- Reworded some commit messages to avoid the term "patches".
- Dropped patch that added explicit rockchip,rk3588-pcie compatible
- Moved !IS_ENABLED(CONFIG_PCIE_ROCKCHIP_DW_HOST) check to proper patch.
- Added comment in front of rk3588 epc_features describing why BAR4 is
  reserved.
- Added another struct epc_features for rk3568 as it does not have the
  ATU regs mapped to BAR4 (like rk3588 does).
- Picked up tags from Rob and Mani. Thank you!
- Link to v2: https://lore.kernel.org/r/20240430-rockchip-pcie-ep-v1-v2-0-a0f5ee2a77b6@kernel.org

Changes in v2:
- Rebased on v4 of the pci-epf-rework series that we depend on.
- Picked up tags from Rob.
- Split dw-rockchip DT binding in to common, RC and EP parts.
- Added support for rk3568 in DT binding and driver.
- Added a new patch that fixed "combined legacy IRQ description".
- Link to v1: https://lore.kernel.org/r/20240424-rockchip-pcie-ep-v1-v1-0-b1a02ddad650@kernel.org

---
Niklas Cassel (13):
      dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific reg-name
      dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific interrupt-names
      dt-bindings: PCI: snps,dw-pcie-ep: Add tx_int{a,b,c,d} legacy irqs
      dt-bindings: PCI: rockchip-dw-pcie: Prepare for Endpoint mode support
      dt-bindings: PCI: rockchip-dw-pcie: Fix description of legacy irq
      dt-bindings: rockchip: Add DesignWare based PCIe Endpoint controller
      PCI: dw-rockchip: Fix weird indentation
      PCI: dw-rockchip: Add rockchip_pcie_get_ltssm() helper
      PCI: dw-rockchip: Refactor the driver to prepare for EP mode
      PCI: dw-rockchip: Add endpoint mode support
      misc: pci_endpoint_test: Add support for rockchip rk3588
      arm64: dts: rockchip: Add PCIe endpoint mode support
      arm64: dts: rockchip: Add rock5b overlays for PCIe endpoint mode

 .../bindings/pci/rockchip-dw-pcie-common.yaml      | 126 +++++++++
 .../bindings/pci/rockchip-dw-pcie-ep.yaml          |  95 +++++++
 .../devicetree/bindings/pci/rockchip-dw-pcie.yaml  |  93 +------
 .../devicetree/bindings/pci/snps,dw-pcie-ep.yaml   |  13 +-
 arch/arm64/boot/dts/rockchip/Makefile              |   5 +
 .../boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso  |  25 ++
 .../dts/rockchip/rk3588-rock-5b-pcie-srns.dtso     |  16 ++
 arch/arm64/boot/dts/rockchip/rk3588.dtsi           |  35 +++
 drivers/misc/pci_endpoint_test.c                   |  11 +
 drivers/pci/controller/dwc/Kconfig                 |  21 +-
 drivers/pci/controller/dwc/Makefile                |   2 +-
 drivers/pci/controller/dwc/pcie-dw-rockchip.c      | 307 +++++++++++++++++++--
 12 files changed, 623 insertions(+), 126 deletions(-)
---
base-commit: 3f7563262863c29368bd17ddeb44e3a95b5195bc
change-id: 20240424-rockchip-pcie-ep-v1-87c78b16d53c

Best regards,

Comments

Niklas Cassel June 17, 2024, 8 a.m. UTC | #1
On Fri, Jun 07, 2024 at 01:14:20PM +0200, Niklas Cassel wrote:
> Hello all,
> 
> This series adds PCIe endpoint mode support for the rockchip rk3588 and
> rk3568 SoCs.
> 
> This series is based on: pci/next
> (git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git)
> 
> This series can also be found in git:
> https://github.com/floatious/linux/commits/rockchip-pcie-ep-v5
> 
> Testing done:
> This series has been tested with two rock5b:s, one running in RC mode and
> one running in EP mode. This series has also been tested with an Intel x86
> host and rock5b running in EP mode.

(snip)

Hello PCI maintainers,

If there is anything more I can do to get this picked up, please tell me.


Kind regards,
Niklas
Krzysztof Wilczyński June 21, 2024, 7:39 p.m. UTC | #2
Hello,

[...]
> If there is anything more I can do to get this picked up, please tell me.

Looks good! As such...

Applied to dt-bindings, thank you!

[01/06] dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific reg-name
        https://git.kernel.org/pci/pci/c/3b287269ab60

[02/06] dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific interrupt-names
        https://git.kernel.org/pci/pci/c/b96353773d24

[03/06] dt-bindings: PCI: snps,dw-pcie-ep: Add tx_int{a,b,c,d} legacy IRQs
        https://git.kernel.org/pci/pci/c/6f308c017c27

[04/06] dt-bindings: PCI: rockchip-dw-pcie: Prepare for Endpoint mode support
        https://git.kernel.org/pci/pci/c/9b0b9b588c00

[05/06] dt-bindings: PCI: rockchip-dw-pcie: Fix description of legacy IRQ
        https://git.kernel.org/pci/pci/c/5f262f67cbc5

[06/06] dt-bindings: rockchip: Add DesignWare based PCIe Endpoint controller
        https://git.kernel.org/pci/pci/c/ff36edde817e

Applied to controller/rockchip, thank you!

[01/04] PCI: dw-rockchip: Fix weird indentation
        https://git.kernel.org/pci/pci/c/e7e8872191af

[02/04] PCI: dw-rockchip: Add rockchip_pcie_get_ltssm() helper
        https://git.kernel.org/pci/pci/c/cbb2d4ae3fdc

[03/04] PCI: dw-rockchip: Add endpoint mode support
        https://git.kernel.org/pci/pci/c/67fe449bcd85

[04/04] PCI: dw-rockchip: Refactor the driver to prepare for EP mode
        https://git.kernel.org/pci/pci/c/ecdc98a3a912

Applied to endpoint, thank you!

[1/1] misc: pci_endpoint_test: Add support for Rockchip rk3588
      https://git.kernel.org/pci/pci/c/657463e393d1

	Krzysztof
Niklas Cassel June 22, 2024, 12:10 p.m. UTC | #3
Krzysztof,
thank you very much for applying!

Heiko,
now when the DT-binding and driver has been queued for 6.11,
is there any chance of getting patches 12/13 and 13/13 applied
to the linux-rockchip tree?


Kind regards,
Niklas
Niklas Cassel June 22, 2024, 1:39 p.m. UTC | #4
On Sat, Jun 22, 2024 at 04:39:37AM +0900, Krzysztof Wilczyński wrote:
> Hello,
>
> [...]
> > If there is anything more I can do to get this picked up, please tell me.
>
> Looks good! As such...
>
> Applied to controller/rockchip, thank you!
>
> [01/04] PCI: dw-rockchip: Fix weird indentation
>         https://git.kernel.org/pci/pci/c/e7e8872191af
>
> [02/04] PCI: dw-rockchip: Add rockchip_pcie_get_ltssm() helper
>         https://git.kernel.org/pci/pci/c/cbb2d4ae3fdc
>
> [03/04] PCI: dw-rockchip: Add endpoint mode support
>         https://git.kernel.org/pci/pci/c/67fe449bcd85
>
> [04/04] PCI: dw-rockchip: Refactor the driver to prepare for EP mode
>         https://git.kernel.org/pci/pci/c/ecdc98a3a912

Krzysztof,

unfortunately, the controller/rockchip branch currently doesn't build:

drivers/pci/controller/dwc/pcie-dw-rockchip.c: In function ‘rockchip_pcie_ep_sys_irq_thread’:
drivers/pci/controller/dwc/pcie-dw-rockchip.c:407:17: error: implicit declaration of function ‘dw_pcie_ep_linkdown’;
	did you mean ‘dw_pcie_ep_linkup’? [-Wimplicit-function-declaration]
  407 |                 dw_pcie_ep_linkdown(&pci->ep);
      |                 ^~~~~~~~~~~~~~~~~~~
      |                 dw_pcie_ep_linkup


Could you possibly include the commit:
3d2e425263e2 ("PCI: dwc: ep: Add a generic dw_pcie_ep_linkdown() API to handle Link Down event")
from the controller/dwc branch in the controller/rockchip as well,
or rebase the controller/rockchip branch on top of the controller/dwc branch,
or merge the controller/dwc branch to the controller/rockchip branch?



Additionally, since you picked up Mani's series which removes
dw_pcie_ep_init_notify() on the controller/dwc branch:
9eba2f70362f ("PCI: dwc: ep: Remove dw_pcie_ep_init_notify() wrapper")

You will need to pick up this patch as well:
https://lore.kernel.org/linux-pci/20240622132024.2927799-2-cassel@kernel.org/T/#u
Otherwise there will be a build error when merging the controller/dwc
and the controller/rockchip branch to for-next.
The patch that I sent out can be picked up to the controller/rockchip right
now (since the API that Mani is switching to already exists in Linus's tree).



May I ask why all the branches for the different DWC glue drivers are not
based on the controller/dwc branch?
They are obviously going to be tightly related.


Kind regards,
Niklas
Krzysztof Wilczyński June 22, 2024, 3:43 p.m. UTC | #5
Hello,

[...]
> Could you possibly include the commit:
> 3d2e425263e2 ("PCI: dwc: ep: Add a generic dw_pcie_ep_linkdown() API to handle Link Down event")
> from the controller/dwc branch in the controller/rockchip as well,
> or rebase the controller/rockchip branch on top of the controller/dwc branch,
> or merge the controller/dwc branch to the controller/rockchip branch?
> 

Done.

> Additionally, since you picked up Mani's series which removes
> dw_pcie_ep_init_notify() on the controller/dwc branch:
> 9eba2f70362f ("PCI: dwc: ep: Remove dw_pcie_ep_init_notify() wrapper")
> 
> You will need to pick up this patch as well:
> https://lore.kernel.org/linux-pci/20240622132024.2927799-2-cassel@kernel.org/T/#u
> Otherwise there will be a build error when merging the controller/dwc
> and the controller/rockchip branch to for-next.
> The patch that I sent out can be picked up to the controller/rockchip right
> now (since the API that Mani is switching to already exists in Linus's tree).

Done.

Hopefully, this settles things for a bit.

> May I ask why all the branches for the different DWC glue drivers are not
> based on the controller/dwc branch?

No worries.

> They are obviously going to be tightly related.

Normally, we prefer to apply things to specific topic branches, but I will
revisit this approach going forward, since changes between Endpoint, DWC
and specific controller drivers are often tightly coupled, as you noted,
which can make things a bit of a mess, unnecessarily.

We are going to do some clean up once Bjorn sends his Pull Request.

	Krzysztof
Niklas Cassel June 22, 2024, 4:34 p.m. UTC | #6
On Sun, Jun 23, 2024 at 12:43:24AM +0900, Krzysztof Wilczyński wrote:
> Hello,
> 
> [...]
> > Could you possibly include the commit:
> > 3d2e425263e2 ("PCI: dwc: ep: Add a generic dw_pcie_ep_linkdown() API to handle Link Down event")
> > from the controller/dwc branch in the controller/rockchip as well,
> > or rebase the controller/rockchip branch on top of the controller/dwc branch,
> > or merge the controller/dwc branch to the controller/rockchip branch?
> > 
> 
> Done.
> 
> > Additionally, since you picked up Mani's series which removes
> > dw_pcie_ep_init_notify() on the controller/dwc branch:
> > 9eba2f70362f ("PCI: dwc: ep: Remove dw_pcie_ep_init_notify() wrapper")
> > 
> > You will need to pick up this patch as well:
> > https://lore.kernel.org/linux-pci/20240622132024.2927799-2-cassel@kernel.org/T/#u
> > Otherwise there will be a build error when merging the controller/dwc
> > and the controller/rockchip branch to for-next.
> > The patch that I sent out can be picked up to the controller/rockchip right
> > now (since the API that Mani is switching to already exists in Linus's tree).
> 
> Done.
> 
> Hopefully, this settles things for a bit.

Everything looks good! :)

I'm glad that we got this sorted quickly, thank you Krzysztof!


Kind regards,
Niklas
Heiko Stuebner June 26, 2024, 3:32 p.m. UTC | #7
On Fri, 07 Jun 2024 13:14:20 +0200, Niklas Cassel wrote:
> This series adds PCIe endpoint mode support for the rockchip rk3588 and
> rk3568 SoCs.
> 
> This series is based on: pci/next
> (git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git)
> 
> This series can also be found in git:
> https://github.com/floatious/linux/commits/rockchip-pcie-ep-v5
> 
> [...]

Applied, thanks!

[12/13] arm64: dts: rockchip: Add PCIe endpoint mode support
        commit: 2fe9fe4e54f5763b8b681478dda9ac61fd42ecaf
[13/13] arm64: dts: rockchip: Add rock5b overlays for PCIe endpoint mode
        commit: 41367db58cbf51ecb89ca017b7473688345caa7b

I've dropped the overlay-symbol-enablement for now.
As this creates massive size increases there have actually
been concerns of things like TF-A getting overwhelmed by
the size if I remember correctly.

In any case, right now we don't have an established way on
how to handle overlay symbold for Rockchip boards.

For example broadcom enables symbols for all DTs, Nvidia and TI do
it for select boards only, while for example Mediatek and Freescale
do not handle symbols at all right now.

So I'll just postpone that decision for a bit.


Best regards,
Niklas Cassel June 26, 2024, 6:13 p.m. UTC | #8
On Wed, Jun 26, 2024 at 05:32:49PM +0200, Heiko Stuebner wrote:
> On Fri, 07 Jun 2024 13:14:20 +0200, Niklas Cassel wrote:
> > This series adds PCIe endpoint mode support for the rockchip rk3588 and
> > rk3568 SoCs.
> > 
> > This series is based on: pci/next
> > (git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git)
> > 
> > This series can also be found in git:
> > https://github.com/floatious/linux/commits/rockchip-pcie-ep-v5
> > 
> > [...]
> 
> Applied, thanks!
> 
> [12/13] arm64: dts: rockchip: Add PCIe endpoint mode support
>         commit: 2fe9fe4e54f5763b8b681478dda9ac61fd42ecaf
> [13/13] arm64: dts: rockchip: Add rock5b overlays for PCIe endpoint mode
>         commit: 41367db58cbf51ecb89ca017b7473688345caa7b
> 
> I've dropped the overlay-symbol-enablement for now.
> As this creates massive size increases there have actually
> been concerns of things like TF-A getting overwhelmed by
> the size if I remember correctly.
> 
> In any case, right now we don't have an established way on
> how to handle overlay symbold for Rockchip boards.
> 
> For example broadcom enables symbols for all DTs, Nvidia and TI do
> it for select boards only, while for example Mediatek and Freescale
> do not handle symbols at all right now.
> 
> So I'll just postpone that decision for a bit.

Okay, I see your argument.


Thank you for applying, I just realized that rk3588.dtsi has been renamed to
rk3588-extra.dtsi, so I was about to rebase and resend these two patches.
The conflict was trivial, and it looks correct in your tree, so thanks a lot
for fixing this up!


Kind regards,
Niklas