| Message ID | 20240623110753.141400-4-quic_akhilpo@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Support for Adreno X1-85 GPU | expand |
On 23/06/2024 13:06, Akhil P Oommen wrote: > Add the necessary dt nodes for gpu support in X1E80100. > > Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> > --- > + gmu: gmu@3d6a000 { > + compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu"; > + reg = <0x0 0x03d50000 0x0 0x10000>, > + <0x0 0x03d6a000 0x0 0x35000>, > + <0x0 0x0b280000 0x0 0x10000>; > + reg-names = "rscc", "gmu", "gmu_pdc"; Really, please start testing your patches. Your internal instructions tells you to do that, so please follow it carefully. Don't use the community as the tool, because you do not want to run checks and investigate results. NAK. Best regards, Krzysztof
On Sun, Jun 23, 2024 at 01:17:16PM +0200, Krzysztof Kozlowski wrote: > On 23/06/2024 13:06, Akhil P Oommen wrote: > > Add the necessary dt nodes for gpu support in X1E80100. > > > > Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> > > --- > > + gmu: gmu@3d6a000 { > > + compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu"; > > + reg = <0x0 0x03d50000 0x0 0x10000>, > > + <0x0 0x03d6a000 0x0 0x35000>, > > + <0x0 0x0b280000 0x0 0x10000>; > > + reg-names = "rscc", "gmu", "gmu_pdc"; > > Really, please start testing your patches. Your internal instructions > tells you to do that, so please follow it carefully. Don't use the > community as the tool, because you do not want to run checks and > investigate results. This was obviously tested before (and retested now) and everything works. I am confused about what you meant. Could you please elaborate a bit? The device and the compilation/test setup is new for me, so I am wondering if I made any silly mistake! -Akhil. > > NAK. > > Best regards, > Krzysztof >
On 23/06/2024 14:28, Akhil P Oommen wrote: > On Sun, Jun 23, 2024 at 01:17:16PM +0200, Krzysztof Kozlowski wrote: >> On 23/06/2024 13:06, Akhil P Oommen wrote: >>> Add the necessary dt nodes for gpu support in X1E80100. >>> >>> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> >>> --- >>> + gmu: gmu@3d6a000 { >>> + compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu"; >>> + reg = <0x0 0x03d50000 0x0 0x10000>, >>> + <0x0 0x03d6a000 0x0 0x35000>, >>> + <0x0 0x0b280000 0x0 0x10000>; >>> + reg-names = "rscc", "gmu", "gmu_pdc"; >> >> Really, please start testing your patches. Your internal instructions >> tells you to do that, so please follow it carefully. Don't use the >> community as the tool, because you do not want to run checks and >> investigate results. > > This was obviously tested before (and retested now) and everything works. I am > confused about what you meant. Could you please elaborate a bit? The device > and the compilation/test setup is new for me, so I am wondering if I > made any silly mistake! Eh, your DTS is not correct, but this could not be pointed out by tests, because the binding does not work. :( I'll fix up the binding and then please test on top of my patch (see your internal guideline about necessary tests before sending any binding or DTS patch). Best regards, Krzysztof
On Sun, Jun 23, 2024 at 02:53:17PM +0200, Krzysztof Kozlowski wrote: > On 23/06/2024 14:28, Akhil P Oommen wrote: > > On Sun, Jun 23, 2024 at 01:17:16PM +0200, Krzysztof Kozlowski wrote: > >> On 23/06/2024 13:06, Akhil P Oommen wrote: > >>> Add the necessary dt nodes for gpu support in X1E80100. > >>> > >>> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> > >>> --- > >>> + gmu: gmu@3d6a000 { > >>> + compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu"; > >>> + reg = <0x0 0x03d50000 0x0 0x10000>, > >>> + <0x0 0x03d6a000 0x0 0x35000>, > >>> + <0x0 0x0b280000 0x0 0x10000>; > >>> + reg-names = "rscc", "gmu", "gmu_pdc"; > >> > >> Really, please start testing your patches. Your internal instructions > >> tells you to do that, so please follow it carefully. Don't use the > >> community as the tool, because you do not want to run checks and > >> investigate results. > > > > This was obviously tested before (and retested now) and everything works. I am > > confused about what you meant. Could you please elaborate a bit? The device > > and the compilation/test setup is new for me, so I am wondering if I > > made any silly mistake! > > Eh, your DTS is not correct, but this could not be pointed out by tests, > because the binding does not work. :( I reordered both "reg" and "reg-names" arrays based on the address. Not sure if that is what we are talking about here. Gpu driver uses platform_get_resource_byname() to query mmio resources. I will retest dt-bindings and dts checks after picking the patches you just posted and report back. Is the schema supposed to enforce strict order? -Akhil. > > I'll fix up the binding and then please test on top of my patch (see > your internal guideline about necessary tests before sending any binding > or DTS patch). > > Best regards, > Krzysztof >
On 23/06/2024 17:16, Akhil P Oommen wrote: > On Sun, Jun 23, 2024 at 02:53:17PM +0200, Krzysztof Kozlowski wrote: >> On 23/06/2024 14:28, Akhil P Oommen wrote: >>> On Sun, Jun 23, 2024 at 01:17:16PM +0200, Krzysztof Kozlowski wrote: >>>> On 23/06/2024 13:06, Akhil P Oommen wrote: >>>>> Add the necessary dt nodes for gpu support in X1E80100. >>>>> >>>>> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> >>>>> --- >>>>> + gmu: gmu@3d6a000 { >>>>> + compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu"; >>>>> + reg = <0x0 0x03d50000 0x0 0x10000>, >>>>> + <0x0 0x03d6a000 0x0 0x35000>, >>>>> + <0x0 0x0b280000 0x0 0x10000>; >>>>> + reg-names = "rscc", "gmu", "gmu_pdc"; >>>> >>>> Really, please start testing your patches. Your internal instructions >>>> tells you to do that, so please follow it carefully. Don't use the >>>> community as the tool, because you do not want to run checks and >>>> investigate results. >>> >>> This was obviously tested before (and retested now) and everything works. I am >>> confused about what you meant. Could you please elaborate a bit? The device >>> and the compilation/test setup is new for me, so I am wondering if I >>> made any silly mistake! >> >> Eh, your DTS is not correct, but this could not be pointed out by tests, >> because the binding does not work. :( > > I reordered both "reg" and "reg-names" arrays based on the address. Not sure if > that is what we are talking about here. Gpu driver uses platform_get_resource_byname() > to query mmio resources. > > I will retest dt-bindings and dts checks after picking the patches you > just posted and report back. Is the schema supposed to enforce strict > order? Yes, because the lists are strictly ordered (with exceptions). Best regards, Krzysztof
On Sun, Jun 23, 2024 at 08:46:30PM GMT, Akhil P Oommen wrote: > On Sun, Jun 23, 2024 at 02:53:17PM +0200, Krzysztof Kozlowski wrote: > > On 23/06/2024 14:28, Akhil P Oommen wrote: > > > On Sun, Jun 23, 2024 at 01:17:16PM +0200, Krzysztof Kozlowski wrote: > > >> On 23/06/2024 13:06, Akhil P Oommen wrote: > > >>> Add the necessary dt nodes for gpu support in X1E80100. > > >>> > > >>> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> > > >>> --- > > >>> + gmu: gmu@3d6a000 { > > >>> + compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu"; > > >>> + reg = <0x0 0x03d50000 0x0 0x10000>, > > >>> + <0x0 0x03d6a000 0x0 0x35000>, > > >>> + <0x0 0x0b280000 0x0 0x10000>; > > >>> + reg-names = "rscc", "gmu", "gmu_pdc"; > > >> > > >> Really, please start testing your patches. Your internal instructions > > >> tells you to do that, so please follow it carefully. Don't use the > > >> community as the tool, because you do not want to run checks and > > >> investigate results. > > > > > > This was obviously tested before (and retested now) and everything works. I am > > > confused about what you meant. Could you please elaborate a bit? The device > > > and the compilation/test setup is new for me, so I am wondering if I > > > made any silly mistake! > > > > Eh, your DTS is not correct, but this could not be pointed out by tests, > > because the binding does not work. :( > > I reordered both "reg" and "reg-names" arrays based on the address. The @3d6a000 should match the first reg entry. > Not sure if > that is what we are talking about here. Gpu driver uses platform_get_resource_byname() > to query mmio resources. > > I will retest dt-bindings and dts checks after picking the patches you > just posted and report back. Is the schema supposed to enforce strict > order? In your second hunk in patch 1, you are defining the order of reg, reg-names, clocks, and clock-names. This creates an ABI between DTB and implementation where ordering is significant - regardless of Linux using platform_get_resource_byname(). Regards, Bjorn > > -Akhil. > > > > I'll fix up the binding and then please test on top of my patch (see > > your internal guideline about necessary tests before sending any binding > > or DTS patch). > > > > Best regards, > > Krzysztof > >
On Sun, Jun 23, 2024 at 03:40:06PM -0500, Bjorn Andersson wrote: > On Sun, Jun 23, 2024 at 08:46:30PM GMT, Akhil P Oommen wrote: > > On Sun, Jun 23, 2024 at 02:53:17PM +0200, Krzysztof Kozlowski wrote: > > > On 23/06/2024 14:28, Akhil P Oommen wrote: > > > > On Sun, Jun 23, 2024 at 01:17:16PM +0200, Krzysztof Kozlowski wrote: > > > >> On 23/06/2024 13:06, Akhil P Oommen wrote: > > > >>> Add the necessary dt nodes for gpu support in X1E80100. > > > >>> > > > >>> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> > > > >>> --- > > > >>> + gmu: gmu@3d6a000 { > > > >>> + compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu"; > > > >>> + reg = <0x0 0x03d50000 0x0 0x10000>, > > > >>> + <0x0 0x03d6a000 0x0 0x35000>, > > > >>> + <0x0 0x0b280000 0x0 0x10000>; > > > >>> + reg-names = "rscc", "gmu", "gmu_pdc"; > > > >> > > > >> Really, please start testing your patches. Your internal instructions > > > >> tells you to do that, so please follow it carefully. Don't use the > > > >> community as the tool, because you do not want to run checks and > > > >> investigate results. > > > > > > > > This was obviously tested before (and retested now) and everything works. I am > > > > confused about what you meant. Could you please elaborate a bit? The device > > > > and the compilation/test setup is new for me, so I am wondering if I > > > > made any silly mistake! > > > > > > Eh, your DTS is not correct, but this could not be pointed out by tests, > > > because the binding does not work. :( > > > > I reordered both "reg" and "reg-names" arrays based on the address. > > The @3d6a000 should match the first reg entry. > > > Not sure if > > that is what we are talking about here. Gpu driver uses platform_get_resource_byname() > > to query mmio resources. > > > > I will retest dt-bindings and dts checks after picking the patches you > > just posted and report back. Is the schema supposed to enforce strict > > order? > > In your second hunk in patch 1, you are defining the order of reg, > reg-names, clocks, and clock-names. This creates an ABI between DTB and > implementation where ordering is significant - regardless of Linux using > platform_get_resource_byname(). I will revert this to the original order. Thanks for the clarification, Bjorn/Krzysztof. -Akhil. > > Regards, > Bjorn > > > > > -Akhil. > > > > > > I'll fix up the binding and then please test on top of my patch (see > > > your internal guideline about necessary tests before sending any binding > > > or DTS patch). > > > > > > Best regards, > > > Krzysztof > > >
On Sun, Jun 23, 2024 at 04:36:30PM GMT, Akhil P Oommen wrote: > Add the necessary dt nodes for gpu support in X1E80100. > > Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> > --- > > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 195 +++++++++++++++++++++++++ > 1 file changed, 195 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > index 5f90a0b3c016..3e887286bab4 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > @@ -6,6 +6,7 @@ > #include <dt-bindings/clock/qcom,rpmh.h> > #include <dt-bindings/clock/qcom,x1e80100-dispcc.h> > #include <dt-bindings/clock/qcom,x1e80100-gcc.h> > +#include <dt-bindings/clock/qcom,x1e80100-gpucc.h> > #include <dt-bindings/clock/qcom,x1e80100-tcsr.h> > #include <dt-bindings/dma/qcom-gpi.h> > #include <dt-bindings/interconnect/qcom,icc.h> > + gmu: gmu@3d6a000 { > + compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu"; > + reg = <0x0 0x03d50000 0x0 0x10000>, > + <0x0 0x03d6a000 0x0 0x35000>, > + <0x0 0x0b280000 0x0 0x10000>; > + reg-names = "rscc", "gmu", "gmu_pdc"; Ther @address should match the first resource defined for a device. > +
On 6/23/24 13:06, Akhil P Oommen wrote: > Add the necessary dt nodes for gpu support in X1E80100. > > Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> > --- [...] > + > + opp-1100000000 { > + opp-hz = /bits/ 64 <1100000000>; > + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; > + opp-peak-kBps = <16500000>; No speedbins? Konrad
On Mon, Jun 24, 2024 at 12:23:42AM +0300, Dmitry Baryshkov wrote: > On Sun, Jun 23, 2024 at 04:36:30PM GMT, Akhil P Oommen wrote: > > Add the necessary dt nodes for gpu support in X1E80100. > > > > Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> > > --- > > > > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 195 +++++++++++++++++++++++++ > > 1 file changed, 195 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > > index 5f90a0b3c016..3e887286bab4 100644 > > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > > @@ -6,6 +6,7 @@ > > #include <dt-bindings/clock/qcom,rpmh.h> > > #include <dt-bindings/clock/qcom,x1e80100-dispcc.h> > > #include <dt-bindings/clock/qcom,x1e80100-gcc.h> > > +#include <dt-bindings/clock/qcom,x1e80100-gpucc.h> > > #include <dt-bindings/clock/qcom,x1e80100-tcsr.h> > > #include <dt-bindings/dma/qcom-gpi.h> > > #include <dt-bindings/interconnect/qcom,icc.h> > > > > + gmu: gmu@3d6a000 { > > + compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu"; > > + reg = <0x0 0x03d50000 0x0 0x10000>, > > + <0x0 0x03d6a000 0x0 0x35000>, > > + <0x0 0x0b280000 0x0 0x10000>; > > + reg-names = "rscc", "gmu", "gmu_pdc"; > > Ther @address should match the first resource defined for a device. I will reorder this and move gmu to first. -Akhil. > > > + > -- > With best wishes > Dmitry
On Mon, Jun 24, 2024 at 03:57:35PM +0200, Konrad Dybcio wrote: > > > On 6/23/24 13:06, Akhil P Oommen wrote: > > Add the necessary dt nodes for gpu support in X1E80100. > > > > Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> > > --- > > [...] > > > + > > + opp-1100000000 { > > + opp-hz = /bits/ 64 <1100000000>; > > + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; > > + opp-peak-kBps = <16500000>; > > No speedbins? Coming soon! I am waiting for some confirmations on some SKU related data. This is the lowest Fmax among all SKUs which we can safely enable for now. -Akhil. > > Konrad
On 26.06.2024 11:04 PM, Akhil P Oommen wrote: > On Mon, Jun 24, 2024 at 03:57:35PM +0200, Konrad Dybcio wrote: >> >> >> On 6/23/24 13:06, Akhil P Oommen wrote: >>> Add the necessary dt nodes for gpu support in X1E80100. >>> >>> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> >>> --- >> >> [...] >> >>> + >>> + opp-1100000000 { >>> + opp-hz = /bits/ 64 <1100000000>; >>> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; >>> + opp-peak-kBps = <16500000>; >> >> No speedbins? > > Coming soon! I am waiting for some confirmations on some SKU related > data. This is the lowest Fmax among all SKUs which we can safely enable > for now. Sounds good, thanks Konrad
Hi Akhil, kernel test robot noticed the following build warnings: [auto build test WARNING on robh/for-next] [also build test WARNING on drm-intel/for-linux-next drm-intel/for-linux-next-fixes drm-tip/drm-tip linus/master v6.10-rc5] [cannot apply to next-20240626] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Akhil-P-Oommen/dt-bindings-display-msm-gmu-Add-Adreno-X185-GMU/20240626-061111 base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next patch link: https://lore.kernel.org/r/20240623110753.141400-4-quic_akhilpo%40quicinc.com patch subject: [PATCH v1 3/3] arm64: dts: qcom: x1e80100: Add gpu support config: arm64-randconfig-051-20240627 (https://download.01.org/0day-ci/archive/20240627/202406271442.d4CbiZMW-lkp@intel.com/config) compiler: clang version 19.0.0git (https://github.com/llvm/llvm-project ad79a14c9e5ec4a369eed4adf567c22cc029863f) dtschema version: 2024.6.dev1+g833054f reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240627/202406271442.d4CbiZMW-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202406271442.d4CbiZMW-lkp@intel.com/ dtcheck warnings: (new ones prefixed by >>) arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: phy@fd5000: 'vdda-pll-supply' is a required property from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml# arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: phy@fda000: 'vdda-phy-supply' is a required property from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml# arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: phy@fda000: 'vdda-pll-supply' is a required property from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml# arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: phy@fdf000: 'vdda-phy-supply' is a required property from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml# arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: phy@fdf000: 'vdda-pll-supply' is a required property from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml# >> arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: iommu@3da0000: compatible: 'oneOf' conditional failed, one must be fixed: ['qcom,x1e80100-smmu-500', 'qcom,adreno-smmu', 'qcom,smmu-500', 'arm,mmu-500'] is too long 'qcom,x1e80100-smmu-500' is not one of ['qcom,msm8996-smmu-v2', 'qcom,msm8998-smmu-v2', 'qcom,sdm630-smmu-v2', 'qcom,sm6375-smmu-v2'] 'qcom,x1e80100-smmu-500' is not one of ['qcom,qcm2290-smmu-500', 'qcom,sc7180-smmu-500', 'qcom,sc7280-smmu-500', 'qcom,sc8180x-smmu-500', 'qcom,sc8280xp-smmu-500', 'qcom,sdm845-smmu-500', 'qcom,sm6115-smmu-500', 'qcom,sm6350-smmu-500', 'qcom,sm6375-smmu-500', 'qcom,sm8150-smmu-500', 'qcom,sm8250-smmu-500', 'qcom,sm8350-smmu-500', 'qcom,sm8450-smmu-500'] 'qcom,x1e80100-smmu-500' is not one of ['qcom,qcm2290-smmu-500', 'qcom,sa8775p-smmu-500', 'qcom,sc7280-smmu-500', 'qcom,sc8280xp-smmu-500', 'qcom,sm6115-smmu-500', 'qcom,sm6125-smmu-500', 'qcom,sm8150-smmu-500', 'qcom,sm8250-smmu-500', 'qcom,sm8350-smmu-500', 'qcom,sm8450-smmu-500', 'qcom,sm8550-smmu-500', 'qcom,sm8650-smmu-500'] 'qcom,x1e80100-smmu-500' is not one of ['qcom,sc7280-smmu-500', 'qcom,sm8150-smmu-500', 'qcom,sm8250-smmu-500'] 'qcom,x1e80100-smmu-500' is not one of ['qcom,msm8996-smmu-v2', 'qcom,sc7180-smmu-v2', 'qcom,sdm630-smmu-v2', 'qcom,sdm845-smmu-v2', 'qcom,sm6350-smmu-v2', 'qcom,sm7150-smmu-v2'] 'qcom,sdm845-smmu-v2' was expected 'marvell,ap806-smmu-500' was expected 'qcom,x1e80100-smmu-500' is not one of ['nvidia,tegra186-smmu', 'nvidia,tegra194-smmu', 'nvidia,tegra234-smmu'] 'arm,mmu-500' was expected 'qcom,x1e80100-smmu-500' is not one of ['arm,mmu-400', 'arm,mmu-401'] 'qcom,x1e80100-smmu-500' is not one of ['arm,smmu-v1', 'arm,smmu-v2', 'arm,mmu-400', 'arm,mmu-401', 'arm,mmu-500', 'cavium,smmu-v2'] 'qcom,smmu-v2' was expected 'qcom,smmu-500' was expected 'nvidia,smmu-500' was expected 'arm,smmu-v2' was expected 'arm,smmu-v1' was expected from schema $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# >> arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: iommu@3da0000: clock-names: False schema does not allow ['hlos', 'bus', 'iface', 'ahb'] from schema $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# >> arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: iommu@3da0000: clocks: False schema does not allow [[150, 14], [51, 55], [51, 56], [150, 0]] from schema $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: usb@a2f8800: interrupt-names: ['pwr_event', 'dp_hs_phy_irq', 'dm_hs_phy_irq'] is too short from schema $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: /soc@0/arbiter@c400000/spmi@c432000/pmic@7: failed to match any schema with compatible: ['qcom,smb2360', 'qcom,spmi-pmic'] arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: /soc@0/arbiter@c400000/spmi@c432000/pmic@a: failed to match any schema with compatible: ['qcom,smb2360', 'qcom,spmi-pmic'] arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: /soc@0/arbiter@c400000/spmi@c432000/pmic@b: failed to match any schema with compatible: ['qcom,smb2360', 'qcom,spmi-pmic'] -- arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: phy@fd5000: 'vdda-pll-supply' is a required property from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: phy@fda000: 'vdda-phy-supply' is a required property from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: phy@fda000: 'vdda-pll-supply' is a required property from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: phy@fdf000: 'vdda-phy-supply' is a required property from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: phy@fdf000: 'vdda-pll-supply' is a required property from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml# >> arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: iommu@3da0000: compatible: 'oneOf' conditional failed, one must be fixed: ['qcom,x1e80100-smmu-500', 'qcom,adreno-smmu', 'qcom,smmu-500', 'arm,mmu-500'] is too long 'qcom,x1e80100-smmu-500' is not one of ['qcom,msm8996-smmu-v2', 'qcom,msm8998-smmu-v2', 'qcom,sdm630-smmu-v2', 'qcom,sm6375-smmu-v2'] 'qcom,x1e80100-smmu-500' is not one of ['qcom,qcm2290-smmu-500', 'qcom,sc7180-smmu-500', 'qcom,sc7280-smmu-500', 'qcom,sc8180x-smmu-500', 'qcom,sc8280xp-smmu-500', 'qcom,sdm845-smmu-500', 'qcom,sm6115-smmu-500', 'qcom,sm6350-smmu-500', 'qcom,sm6375-smmu-500', 'qcom,sm8150-smmu-500', 'qcom,sm8250-smmu-500', 'qcom,sm8350-smmu-500', 'qcom,sm8450-smmu-500'] 'qcom,x1e80100-smmu-500' is not one of ['qcom,qcm2290-smmu-500', 'qcom,sa8775p-smmu-500', 'qcom,sc7280-smmu-500', 'qcom,sc8280xp-smmu-500', 'qcom,sm6115-smmu-500', 'qcom,sm6125-smmu-500', 'qcom,sm8150-smmu-500', 'qcom,sm8250-smmu-500', 'qcom,sm8350-smmu-500', 'qcom,sm8450-smmu-500', 'qcom,sm8550-smmu-500', 'qcom,sm8650-smmu-500'] 'qcom,x1e80100-smmu-500' is not one of ['qcom,sc7280-smmu-500', 'qcom,sm8150-smmu-500', 'qcom,sm8250-smmu-500'] 'qcom,x1e80100-smmu-500' is not one of ['qcom,msm8996-smmu-v2', 'qcom,sc7180-smmu-v2', 'qcom,sdm630-smmu-v2', 'qcom,sdm845-smmu-v2', 'qcom,sm6350-smmu-v2', 'qcom,sm7150-smmu-v2'] 'qcom,sdm845-smmu-v2' was expected 'marvell,ap806-smmu-500' was expected 'qcom,x1e80100-smmu-500' is not one of ['nvidia,tegra186-smmu', 'nvidia,tegra194-smmu', 'nvidia,tegra234-smmu'] 'arm,mmu-500' was expected 'qcom,x1e80100-smmu-500' is not one of ['arm,mmu-400', 'arm,mmu-401'] 'qcom,x1e80100-smmu-500' is not one of ['arm,smmu-v1', 'arm,smmu-v2', 'arm,mmu-400', 'arm,mmu-401', 'arm,mmu-500', 'cavium,smmu-v2'] 'qcom,smmu-v2' was expected 'qcom,smmu-500' was expected 'nvidia,smmu-500' was expected 'arm,smmu-v2' was expected 'arm,smmu-v1' was expected from schema $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# >> arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: iommu@3da0000: clock-names: False schema does not allow ['hlos', 'bus', 'iface', 'ahb'] from schema $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# >> arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: iommu@3da0000: clocks: False schema does not allow [[146, 14], [51, 55], [51, 56], [146, 0]] from schema $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: usb@a2f8800: interrupt-names: ['pwr_event', 'dp_hs_phy_irq', 'dm_hs_phy_irq'] is too short from schema $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: /soc@0/arbiter@c400000/spmi@c432000/pmic@7: failed to match any schema with compatible: ['qcom,smb2360', 'qcom,spmi-pmic'] arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: /soc@0/arbiter@c400000/spmi@c432000/pmic@a: failed to match any schema with compatible: ['qcom,smb2360', 'qcom,spmi-pmic'] arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: /soc@0/arbiter@c400000/spmi@c432000/pmic@b: failed to match any schema with compatible: ['qcom,smb2360', 'qcom,spmi-pmic']
Hi Akhil, kernel test robot noticed the following build warnings: [auto build test WARNING on robh/for-next] [also build test WARNING on drm-intel/for-linux-next drm-intel/for-linux-next-fixes drm-tip/drm-tip linus/master v6.10-rc5] [cannot apply to next-20240626] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Akhil-P-Oommen/dt-bindings-display-msm-gmu-Add-Adreno-X185-GMU/20240626-061111 base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next patch link: https://lore.kernel.org/r/20240623110753.141400-4-quic_akhilpo%40quicinc.com patch subject: [PATCH v1 3/3] arm64: dts: qcom: x1e80100: Add gpu support config: arm64-randconfig-051-20240627 (https://download.01.org/0day-ci/archive/20240628/202406280339.nvI0OrO3-lkp@intel.com/config) compiler: clang version 19.0.0git (https://github.com/llvm/llvm-project ad79a14c9e5ec4a369eed4adf567c22cc029863f) dtschema version: 2024.6.dev2+g3b69bad reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240628/202406280339.nvI0OrO3-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202406280339.nvI0OrO3-lkp@intel.com/ dtcheck warnings: (new ones prefixed by >>) arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: phy@fda000: 'vdda-pll-supply' is a required property from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml# arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: phy@fdf000: 'vdda-phy-supply' is a required property from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml# arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: phy@fdf000: 'vdda-pll-supply' is a required property from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml# arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: gmu@3d6a000: reg-names:0: 'gmu' was expected from schema $id: http://devicetree.org/schemas/display/msm/gmu.yaml# arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: gmu@3d6a000: reg-names:1: 'rscc' was expected from schema $id: http://devicetree.org/schemas/display/msm/gmu.yaml# >> arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: iommu@3da0000: compatible: 'oneOf' conditional failed, one must be fixed: ['qcom,x1e80100-smmu-500', 'qcom,adreno-smmu', 'qcom,smmu-500', 'arm,mmu-500'] is too long 'qcom,x1e80100-smmu-500' is not one of ['qcom,msm8996-smmu-v2', 'qcom,msm8998-smmu-v2', 'qcom,sdm630-smmu-v2', 'qcom,sm6375-smmu-v2'] 'qcom,x1e80100-smmu-500' is not one of ['qcom,qcm2290-smmu-500', 'qcom,sc7180-smmu-500', 'qcom,sc7280-smmu-500', 'qcom,sc8180x-smmu-500', 'qcom,sc8280xp-smmu-500', 'qcom,sdm845-smmu-500', 'qcom,sm6115-smmu-500', 'qcom,sm6350-smmu-500', 'qcom,sm6375-smmu-500', 'qcom,sm8150-smmu-500', 'qcom,sm8250-smmu-500', 'qcom,sm8350-smmu-500', 'qcom,sm8450-smmu-500'] 'qcom,x1e80100-smmu-500' is not one of ['qcom,qcm2290-smmu-500', 'qcom,sa8775p-smmu-500', 'qcom,sc7280-smmu-500', 'qcom,sc8280xp-smmu-500', 'qcom,sm6115-smmu-500', 'qcom,sm6125-smmu-500', 'qcom,sm8150-smmu-500', 'qcom,sm8250-smmu-500', 'qcom,sm8350-smmu-500', 'qcom,sm8450-smmu-500', 'qcom,sm8550-smmu-500', 'qcom,sm8650-smmu-500'] 'qcom,x1e80100-smmu-500' is not one of ['qcom,sc7280-smmu-500', 'qcom,sm8150-smmu-500', 'qcom,sm8250-smmu-500'] 'qcom,x1e80100-smmu-500' is not one of ['qcom,msm8996-smmu-v2', 'qcom,sc7180-smmu-v2', 'qcom,sdm630-smmu-v2', 'qcom,sdm845-smmu-v2', 'qcom,sm6350-smmu-v2', 'qcom,sm7150-smmu-v2'] 'qcom,sdm845-smmu-v2' was expected 'marvell,ap806-smmu-500' was expected 'qcom,x1e80100-smmu-500' is not one of ['nvidia,tegra186-smmu', 'nvidia,tegra194-smmu', 'nvidia,tegra234-smmu'] 'arm,mmu-500' was expected 'qcom,x1e80100-smmu-500' is not one of ['arm,mmu-400', 'arm,mmu-401'] 'qcom,x1e80100-smmu-500' is not one of ['arm,smmu-v1', 'arm,smmu-v2', 'arm,mmu-400', 'arm,mmu-401', 'arm,mmu-500', 'cavium,smmu-v2'] 'qcom,smmu-v2' was expected 'qcom,smmu-500' was expected 'nvidia,smmu-500' was expected 'arm,smmu-v2' was expected 'arm,smmu-v1' was expected from schema $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# >> arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: iommu@3da0000: clock-names: False schema does not allow ['hlos', 'bus', 'iface', 'ahb'] from schema $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# >> arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: iommu@3da0000: clocks: False schema does not allow [[150, 14], [51, 55], [51, 56], [150, 0]] from schema $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: usb@a2f8800: interrupt-names: ['pwr_event', 'dp_hs_phy_irq', 'dm_hs_phy_irq'] is too short from schema $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: pmic@7: compatible:0: 'qcom,smb2360' is not one of ['qcom,pm2250', 'qcom,pm6125', 'qcom,pm6150', 'qcom,pm6150l', 'qcom,pm6350', 'qcom,pm660', 'qcom,pm660l', 'qcom,pm7250b', 'qcom,pm7550ba', 'qcom,pm7325', 'qcom,pm8004', 'qcom,pm8005', 'qcom,pm8009', 'qcom,pm8010', 'qcom,pm8019', 'qcom,pm8028', 'qcom,pm8110', 'qcom,pm8150', 'qcom,pm8150b', 'qcom,pm8150c', 'qcom,pm8150l', 'qcom,pm8226', 'qcom,pm8350', 'qcom,pm8350b', 'qcom,pm8350c', 'qcom,pm8450', 'qcom,pm8550', 'qcom,pm8550b', 'qcom,pm8550ve', 'qcom,pm8550vs', 'qcom,pm8841', 'qcom,pm8909', 'qcom,pm8916', 'qcom,pm8937', 'qcom,pm8941', 'qcom,pm8950', 'qcom,pm8953', 'qcom,pm8994', 'qcom,pm8998', 'qcom,pma8084', 'qcom,pmc8180', 'qcom,pmc8180c', 'qcom,pmd9635', 'qcom,pmi632', 'qcom,pmi8950', 'qcom,pmi8962', 'qcom,pmi8994', 'qcom,pmi8998', 'qcom,pmk8002', 'qcom,pmk8350', 'qcom,pmk8550', 'qcom,pmm8155au', 'qcom,pmm8654au', 'qcom,pmp8074', 'qcom,pmr735a', 'qcom,pmr735b', 'qcom,pmr735d', 'qcom,pms405', 'qcom,pmx55', 'qcom,pmx65', 'qcom,pmx75', 'qcom,smb2351'] from schema $id: http://devicetree.org/schemas/mfd/qcom,spmi-pmic.yaml# arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: /soc@0/arbiter@c400000/spmi@c432000/pmic@7: failed to match any schema with compatible: ['qcom,smb2360', 'qcom,spmi-pmic'] arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: pmic@a: compatible:0: 'qcom,smb2360' is not one of ['qcom,pm2250', 'qcom,pm6125', 'qcom,pm6150', 'qcom,pm6150l', 'qcom,pm6350', 'qcom,pm660', 'qcom,pm660l', 'qcom,pm7250b', 'qcom,pm7550ba', 'qcom,pm7325', 'qcom,pm8004', 'qcom,pm8005', 'qcom,pm8009', 'qcom,pm8010', 'qcom,pm8019', 'qcom,pm8028', 'qcom,pm8110', 'qcom,pm8150', 'qcom,pm8150b', 'qcom,pm8150c', 'qcom,pm8150l', 'qcom,pm8226', 'qcom,pm8350', 'qcom,pm8350b', 'qcom,pm8350c', 'qcom,pm8450', 'qcom,pm8550', 'qcom,pm8550b', 'qcom,pm8550ve', 'qcom,pm8550vs', 'qcom,pm8841', 'qcom,pm8909', 'qcom,pm8916', 'qcom,pm8937', 'qcom,pm8941', 'qcom,pm8950', 'qcom,pm8953', 'qcom,pm8994', 'qcom,pm8998', 'qcom,pma8084', 'qcom,pmc8180', 'qcom,pmc8180c', 'qcom,pmd9635', 'qcom,pmi632', 'qcom,pmi8950', 'qcom,pmi8962', 'qcom,pmi8994', 'qcom,pmi8998', 'qcom,pmk8002', 'qcom,pmk8350', 'qcom,pmk8550', 'qcom,pmm8155au', 'qcom,pmm8654au', 'qcom,pmp8074', 'qcom,pmr735a', 'qcom,pmr735b', 'qcom,pmr735d', 'qcom,pms405', 'qcom,pmx55', 'qcom,pmx65', 'qcom,pmx75', 'qcom,smb2351'] from schema $id: http://devicetree.org/schemas/mfd/qcom,spmi-pmic.yaml# arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: /soc@0/arbiter@c400000/spmi@c432000/pmic@a: failed to match any schema with compatible: ['qcom,smb2360', 'qcom,spmi-pmic'] arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: pmic@b: compatible:0: 'qcom,smb2360' is not one of ['qcom,pm2250', 'qcom,pm6125', 'qcom,pm6150', 'qcom,pm6150l', 'qcom,pm6350', 'qcom,pm660', 'qcom,pm660l', 'qcom,pm7250b', 'qcom,pm7550ba', 'qcom,pm7325', 'qcom,pm8004', 'qcom,pm8005', 'qcom,pm8009', 'qcom,pm8010', 'qcom,pm8019', 'qcom,pm8028', 'qcom,pm8110', 'qcom,pm8150', 'qcom,pm8150b', 'qcom,pm8150c', 'qcom,pm8150l', 'qcom,pm8226', 'qcom,pm8350', 'qcom,pm8350b', 'qcom,pm8350c', 'qcom,pm8450', 'qcom,pm8550', 'qcom,pm8550b', 'qcom,pm8550ve', 'qcom,pm8550vs', 'qcom,pm8841', 'qcom,pm8909', 'qcom,pm8916', 'qcom,pm8937', 'qcom,pm8941', 'qcom,pm8950', 'qcom,pm8953', 'qcom,pm8994', 'qcom,pm8998', 'qcom,pma8084', 'qcom,pmc8180', 'qcom,pmc8180c', 'qcom,pmd9635', 'qcom,pmi632', 'qcom,pmi8950', 'qcom,pmi8962', 'qcom,pmi8994', 'qcom,pmi8998', 'qcom,pmk8002', 'qcom,pmk8350', 'qcom,pmk8550', 'qcom,pmm8155au', 'qcom,pmm8654au', 'qcom,pmp8074', 'qcom,pmr735a', 'qcom,pmr735b', 'qcom,pmr735d', 'qcom,pms405', 'qcom,pmx55', 'qcom,pmx65', 'qcom,pmx75', 'qcom,smb2351'] -- arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: phy@fda000: 'vdda-pll-supply' is a required property from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: phy@fdf000: 'vdda-phy-supply' is a required property from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: phy@fdf000: 'vdda-pll-supply' is a required property from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: gmu@3d6a000: reg-names:0: 'gmu' was expected from schema $id: http://devicetree.org/schemas/display/msm/gmu.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: gmu@3d6a000: reg-names:1: 'rscc' was expected from schema $id: http://devicetree.org/schemas/display/msm/gmu.yaml# >> arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: iommu@3da0000: compatible: 'oneOf' conditional failed, one must be fixed: ['qcom,x1e80100-smmu-500', 'qcom,adreno-smmu', 'qcom,smmu-500', 'arm,mmu-500'] is too long 'qcom,x1e80100-smmu-500' is not one of ['qcom,msm8996-smmu-v2', 'qcom,msm8998-smmu-v2', 'qcom,sdm630-smmu-v2', 'qcom,sm6375-smmu-v2'] 'qcom,x1e80100-smmu-500' is not one of ['qcom,qcm2290-smmu-500', 'qcom,sc7180-smmu-500', 'qcom,sc7280-smmu-500', 'qcom,sc8180x-smmu-500', 'qcom,sc8280xp-smmu-500', 'qcom,sdm845-smmu-500', 'qcom,sm6115-smmu-500', 'qcom,sm6350-smmu-500', 'qcom,sm6375-smmu-500', 'qcom,sm8150-smmu-500', 'qcom,sm8250-smmu-500', 'qcom,sm8350-smmu-500', 'qcom,sm8450-smmu-500'] 'qcom,x1e80100-smmu-500' is not one of ['qcom,qcm2290-smmu-500', 'qcom,sa8775p-smmu-500', 'qcom,sc7280-smmu-500', 'qcom,sc8280xp-smmu-500', 'qcom,sm6115-smmu-500', 'qcom,sm6125-smmu-500', 'qcom,sm8150-smmu-500', 'qcom,sm8250-smmu-500', 'qcom,sm8350-smmu-500', 'qcom,sm8450-smmu-500', 'qcom,sm8550-smmu-500', 'qcom,sm8650-smmu-500'] 'qcom,x1e80100-smmu-500' is not one of ['qcom,sc7280-smmu-500', 'qcom,sm8150-smmu-500', 'qcom,sm8250-smmu-500'] 'qcom,x1e80100-smmu-500' is not one of ['qcom,msm8996-smmu-v2', 'qcom,sc7180-smmu-v2', 'qcom,sdm630-smmu-v2', 'qcom,sdm845-smmu-v2', 'qcom,sm6350-smmu-v2', 'qcom,sm7150-smmu-v2'] 'qcom,sdm845-smmu-v2' was expected 'marvell,ap806-smmu-500' was expected 'qcom,x1e80100-smmu-500' is not one of ['nvidia,tegra186-smmu', 'nvidia,tegra194-smmu', 'nvidia,tegra234-smmu'] 'arm,mmu-500' was expected 'qcom,x1e80100-smmu-500' is not one of ['arm,mmu-400', 'arm,mmu-401'] 'qcom,x1e80100-smmu-500' is not one of ['arm,smmu-v1', 'arm,smmu-v2', 'arm,mmu-400', 'arm,mmu-401', 'arm,mmu-500', 'cavium,smmu-v2'] 'qcom,smmu-v2' was expected 'qcom,smmu-500' was expected 'nvidia,smmu-500' was expected 'arm,smmu-v2' was expected 'arm,smmu-v1' was expected from schema $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# >> arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: iommu@3da0000: clock-names: False schema does not allow ['hlos', 'bus', 'iface', 'ahb'] from schema $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# >> arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: iommu@3da0000: clocks: False schema does not allow [[146, 14], [51, 55], [51, 56], [146, 0]] from schema $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: usb@a2f8800: interrupt-names: ['pwr_event', 'dp_hs_phy_irq', 'dm_hs_phy_irq'] is too short from schema $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: pmic@7: compatible:0: 'qcom,smb2360' is not one of ['qcom,pm2250', 'qcom,pm6125', 'qcom,pm6150', 'qcom,pm6150l', 'qcom,pm6350', 'qcom,pm660', 'qcom,pm660l', 'qcom,pm7250b', 'qcom,pm7550ba', 'qcom,pm7325', 'qcom,pm8004', 'qcom,pm8005', 'qcom,pm8009', 'qcom,pm8010', 'qcom,pm8019', 'qcom,pm8028', 'qcom,pm8110', 'qcom,pm8150', 'qcom,pm8150b', 'qcom,pm8150c', 'qcom,pm8150l', 'qcom,pm8226', 'qcom,pm8350', 'qcom,pm8350b', 'qcom,pm8350c', 'qcom,pm8450', 'qcom,pm8550', 'qcom,pm8550b', 'qcom,pm8550ve', 'qcom,pm8550vs', 'qcom,pm8841', 'qcom,pm8909', 'qcom,pm8916', 'qcom,pm8937', 'qcom,pm8941', 'qcom,pm8950', 'qcom,pm8953', 'qcom,pm8994', 'qcom,pm8998', 'qcom,pma8084', 'qcom,pmc8180', 'qcom,pmc8180c', 'qcom,pmd9635', 'qcom,pmi632', 'qcom,pmi8950', 'qcom,pmi8962', 'qcom,pmi8994', 'qcom,pmi8998', 'qcom,pmk8002', 'qcom,pmk8350', 'qcom,pmk8550', 'qcom,pmm8155au', 'qcom,pmm8654au', 'qcom,pmp8074', 'qcom,pmr735a', 'qcom,pmr735b', 'qcom,pmr735d', 'qcom,pms405', 'qcom,pmx55', 'qcom,pmx65', 'qcom,pmx75', 'qcom,smb2351'] from schema $id: http://devicetree.org/schemas/mfd/qcom,spmi-pmic.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: /soc@0/arbiter@c400000/spmi@c432000/pmic@7: failed to match any schema with compatible: ['qcom,smb2360', 'qcom,spmi-pmic'] arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: pmic@a: compatible:0: 'qcom,smb2360' is not one of ['qcom,pm2250', 'qcom,pm6125', 'qcom,pm6150', 'qcom,pm6150l', 'qcom,pm6350', 'qcom,pm660', 'qcom,pm660l', 'qcom,pm7250b', 'qcom,pm7550ba', 'qcom,pm7325', 'qcom,pm8004', 'qcom,pm8005', 'qcom,pm8009', 'qcom,pm8010', 'qcom,pm8019', 'qcom,pm8028', 'qcom,pm8110', 'qcom,pm8150', 'qcom,pm8150b', 'qcom,pm8150c', 'qcom,pm8150l', 'qcom,pm8226', 'qcom,pm8350', 'qcom,pm8350b', 'qcom,pm8350c', 'qcom,pm8450', 'qcom,pm8550', 'qcom,pm8550b', 'qcom,pm8550ve', 'qcom,pm8550vs', 'qcom,pm8841', 'qcom,pm8909', 'qcom,pm8916', 'qcom,pm8937', 'qcom,pm8941', 'qcom,pm8950', 'qcom,pm8953', 'qcom,pm8994', 'qcom,pm8998', 'qcom,pma8084', 'qcom,pmc8180', 'qcom,pmc8180c', 'qcom,pmd9635', 'qcom,pmi632', 'qcom,pmi8950', 'qcom,pmi8962', 'qcom,pmi8994', 'qcom,pmi8998', 'qcom,pmk8002', 'qcom,pmk8350', 'qcom,pmk8550', 'qcom,pmm8155au', 'qcom,pmm8654au', 'qcom,pmp8074', 'qcom,pmr735a', 'qcom,pmr735b', 'qcom,pmr735d', 'qcom,pms405', 'qcom,pmx55', 'qcom,pmx65', 'qcom,pmx75', 'qcom,smb2351'] from schema $id: http://devicetree.org/schemas/mfd/qcom,spmi-pmic.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: /soc@0/arbiter@c400000/spmi@c432000/pmic@a: failed to match any schema with compatible: ['qcom,smb2360', 'qcom,spmi-pmic'] arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: pmic@b: compatible:0: 'qcom,smb2360' is not one of ['qcom,pm2250', 'qcom,pm6125', 'qcom,pm6150', 'qcom,pm6150l', 'qcom,pm6350', 'qcom,pm660', 'qcom,pm660l', 'qcom,pm7250b', 'qcom,pm7550ba', 'qcom,pm7325', 'qcom,pm8004', 'qcom,pm8005', 'qcom,pm8009', 'qcom,pm8010', 'qcom,pm8019', 'qcom,pm8028', 'qcom,pm8110', 'qcom,pm8150', 'qcom,pm8150b', 'qcom,pm8150c', 'qcom,pm8150l', 'qcom,pm8226', 'qcom,pm8350', 'qcom,pm8350b', 'qcom,pm8350c', 'qcom,pm8450', 'qcom,pm8550', 'qcom,pm8550b', 'qcom,pm8550ve', 'qcom,pm8550vs', 'qcom,pm8841', 'qcom,pm8909', 'qcom,pm8916', 'qcom,pm8937', 'qcom,pm8941', 'qcom,pm8950', 'qcom,pm8953', 'qcom,pm8994', 'qcom,pm8998', 'qcom,pma8084', 'qcom,pmc8180', 'qcom,pmc8180c', 'qcom,pmd9635', 'qcom,pmi632', 'qcom,pmi8950', 'qcom,pmi8962', 'qcom,pmi8994', 'qcom,pmi8998', 'qcom,pmk8002', 'qcom,pmk8350', 'qcom,pmk8550', 'qcom,pmm8155au', 'qcom,pmm8654au', 'qcom,pmp8074', 'qcom,pmr735a', 'qcom,pmr735b', 'qcom,pmr735d', 'qcom,pms405', 'qcom,pmx55', 'qcom,pmx65', 'qcom,pmx75', 'qcom,smb2351']
Hi Akhil, kernel test robot noticed the following build warnings: [auto build test WARNING on robh/for-next] [also build test WARNING on drm-intel/for-linux-next drm-intel/for-linux-next-fixes drm-tip/drm-tip linus/master v6.10-rc5] [cannot apply to next-20240627] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Akhil-P-Oommen/dt-bindings-display-msm-gmu-Add-Adreno-X185-GMU/20240626-061111 base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next patch link: https://lore.kernel.org/r/20240623110753.141400-4-quic_akhilpo%40quicinc.com patch subject: [PATCH v1 3/3] arm64: dts: qcom: x1e80100: Add gpu support config: arm64-randconfig-051-20240627 (https://download.01.org/0day-ci/archive/20240628/202406282158.ogy7XNu2-lkp@intel.com/config) compiler: clang version 19.0.0git (https://github.com/llvm/llvm-project ad79a14c9e5ec4a369eed4adf567c22cc029863f) dtschema version: 2024.6.dev3+g650bf2d reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240628/202406282158.ogy7XNu2-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202406282158.ogy7XNu2-lkp@intel.com/ dtcheck warnings: (new ones prefixed by >>) arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: phy@fda000: 'vdda-pll-supply' is a required property from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml# arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: phy@fdf000: 'vdda-phy-supply' is a required property from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml# arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: phy@fdf000: 'vdda-pll-supply' is a required property from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml# arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: gmu@3d6a000: reg-names:0: 'gmu' was expected from schema $id: http://devicetree.org/schemas/display/msm/gmu.yaml# arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: gmu@3d6a000: reg-names:1: 'rscc' was expected from schema $id: http://devicetree.org/schemas/display/msm/gmu.yaml# >> arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: iommu@3da0000: compatible: 'oneOf' conditional failed, one must be fixed: ['qcom,x1e80100-smmu-500', 'qcom,adreno-smmu', 'qcom,smmu-500', 'arm,mmu-500'] is too long 'qcom,x1e80100-smmu-500' is not one of ['qcom,msm8996-smmu-v2', 'qcom,msm8998-smmu-v2', 'qcom,sdm630-smmu-v2', 'qcom,sm6375-smmu-v2'] 'qcom,x1e80100-smmu-500' is not one of ['qcom,qcm2290-smmu-500', 'qcom,sc7180-smmu-500', 'qcom,sc7280-smmu-500', 'qcom,sc8180x-smmu-500', 'qcom,sc8280xp-smmu-500', 'qcom,sdm845-smmu-500', 'qcom,sm6115-smmu-500', 'qcom,sm6350-smmu-500', 'qcom,sm6375-smmu-500', 'qcom,sm8150-smmu-500', 'qcom,sm8250-smmu-500', 'qcom,sm8350-smmu-500', 'qcom,sm8450-smmu-500'] 'qcom,x1e80100-smmu-500' is not one of ['qcom,qcm2290-smmu-500', 'qcom,sa8775p-smmu-500', 'qcom,sc7280-smmu-500', 'qcom,sc8280xp-smmu-500', 'qcom,sm6115-smmu-500', 'qcom,sm6125-smmu-500', 'qcom,sm8150-smmu-500', 'qcom,sm8250-smmu-500', 'qcom,sm8350-smmu-500', 'qcom,sm8450-smmu-500', 'qcom,sm8550-smmu-500', 'qcom,sm8650-smmu-500'] 'qcom,x1e80100-smmu-500' is not one of ['qcom,sc7280-smmu-500', 'qcom,sm8150-smmu-500', 'qcom,sm8250-smmu-500'] 'qcom,x1e80100-smmu-500' is not one of ['qcom,msm8996-smmu-v2', 'qcom,sc7180-smmu-v2', 'qcom,sdm630-smmu-v2', 'qcom,sdm845-smmu-v2', 'qcom,sm6350-smmu-v2', 'qcom,sm7150-smmu-v2'] 'qcom,sdm845-smmu-v2' was expected 'marvell,ap806-smmu-500' was expected 'qcom,x1e80100-smmu-500' is not one of ['nvidia,tegra186-smmu', 'nvidia,tegra194-smmu', 'nvidia,tegra234-smmu'] 'arm,mmu-500' was expected 'qcom,x1e80100-smmu-500' is not one of ['arm,mmu-400', 'arm,mmu-401'] 'qcom,x1e80100-smmu-500' is not one of ['arm,smmu-v1', 'arm,smmu-v2', 'arm,mmu-400', 'arm,mmu-401', 'arm,mmu-500', 'cavium,smmu-v2'] 'qcom,smmu-v2' was expected 'qcom,smmu-500' was expected 'nvidia,smmu-500' was expected 'arm,smmu-v2' was expected 'arm,smmu-v1' was expected from schema $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# >> arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: iommu@3da0000: clock-names: False schema does not allow ['hlos', 'bus', 'iface', 'ahb'] from schema $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# >> arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: iommu@3da0000: clocks: False schema does not allow [[150, 14], [51, 55], [51, 56], [150, 0]] from schema $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: usb@a2f8800: interrupt-names: ['pwr_event', 'dp_hs_phy_irq', 'dm_hs_phy_irq'] is too short from schema $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: pmic@7: compatible:0: 'qcom,smb2360' is not one of ['qcom,pm2250', 'qcom,pm6125', 'qcom,pm6150', 'qcom,pm6150l', 'qcom,pm6350', 'qcom,pm660', 'qcom,pm660l', 'qcom,pm7250b', 'qcom,pm7550ba', 'qcom,pm7325', 'qcom,pm8004', 'qcom,pm8005', 'qcom,pm8009', 'qcom,pm8010', 'qcom,pm8019', 'qcom,pm8028', 'qcom,pm8110', 'qcom,pm8150', 'qcom,pm8150b', 'qcom,pm8150c', 'qcom,pm8150l', 'qcom,pm8226', 'qcom,pm8350', 'qcom,pm8350b', 'qcom,pm8350c', 'qcom,pm8450', 'qcom,pm8550', 'qcom,pm8550b', 'qcom,pm8550ve', 'qcom,pm8550vs', 'qcom,pm8841', 'qcom,pm8909', 'qcom,pm8916', 'qcom,pm8937', 'qcom,pm8941', 'qcom,pm8950', 'qcom,pm8953', 'qcom,pm8994', 'qcom,pm8998', 'qcom,pma8084', 'qcom,pmc8180', 'qcom,pmc8180c', 'qcom,pmd9635', 'qcom,pmi632', 'qcom,pmi8950', 'qcom,pmi8962', 'qcom,pmi8994', 'qcom,pmi8998', 'qcom,pmk8002', 'qcom,pmk8350', 'qcom,pmk8550', 'qcom,pmm8155au', 'qcom,pmm8654au', 'qcom,pmp8074', 'qcom,pmr735a', 'qcom,pmr735b', 'qcom,pmr735d', 'qcom,pms405', 'qcom,pmx55', 'qcom,pmx65', 'qcom,pmx75', 'qcom,smb2351'] from schema $id: http://devicetree.org/schemas/mfd/qcom,spmi-pmic.yaml# arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: /soc@0/arbiter@c400000/spmi@c432000/pmic@7: failed to match any schema with compatible: ['qcom,smb2360', 'qcom,spmi-pmic'] arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: pmic@a: compatible:0: 'qcom,smb2360' is not one of ['qcom,pm2250', 'qcom,pm6125', 'qcom,pm6150', 'qcom,pm6150l', 'qcom,pm6350', 'qcom,pm660', 'qcom,pm660l', 'qcom,pm7250b', 'qcom,pm7550ba', 'qcom,pm7325', 'qcom,pm8004', 'qcom,pm8005', 'qcom,pm8009', 'qcom,pm8010', 'qcom,pm8019', 'qcom,pm8028', 'qcom,pm8110', 'qcom,pm8150', 'qcom,pm8150b', 'qcom,pm8150c', 'qcom,pm8150l', 'qcom,pm8226', 'qcom,pm8350', 'qcom,pm8350b', 'qcom,pm8350c', 'qcom,pm8450', 'qcom,pm8550', 'qcom,pm8550b', 'qcom,pm8550ve', 'qcom,pm8550vs', 'qcom,pm8841', 'qcom,pm8909', 'qcom,pm8916', 'qcom,pm8937', 'qcom,pm8941', 'qcom,pm8950', 'qcom,pm8953', 'qcom,pm8994', 'qcom,pm8998', 'qcom,pma8084', 'qcom,pmc8180', 'qcom,pmc8180c', 'qcom,pmd9635', 'qcom,pmi632', 'qcom,pmi8950', 'qcom,pmi8962', 'qcom,pmi8994', 'qcom,pmi8998', 'qcom,pmk8002', 'qcom,pmk8350', 'qcom,pmk8550', 'qcom,pmm8155au', 'qcom,pmm8654au', 'qcom,pmp8074', 'qcom,pmr735a', 'qcom,pmr735b', 'qcom,pmr735d', 'qcom,pms405', 'qcom,pmx55', 'qcom,pmx65', 'qcom,pmx75', 'qcom,smb2351'] from schema $id: http://devicetree.org/schemas/mfd/qcom,spmi-pmic.yaml# arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: /soc@0/arbiter@c400000/spmi@c432000/pmic@a: failed to match any schema with compatible: ['qcom,smb2360', 'qcom,spmi-pmic'] arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: pmic@b: compatible:0: 'qcom,smb2360' is not one of ['qcom,pm2250', 'qcom,pm6125', 'qcom,pm6150', 'qcom,pm6150l', 'qcom,pm6350', 'qcom,pm660', 'qcom,pm660l', 'qcom,pm7250b', 'qcom,pm7550ba', 'qcom,pm7325', 'qcom,pm8004', 'qcom,pm8005', 'qcom,pm8009', 'qcom,pm8010', 'qcom,pm8019', 'qcom,pm8028', 'qcom,pm8110', 'qcom,pm8150', 'qcom,pm8150b', 'qcom,pm8150c', 'qcom,pm8150l', 'qcom,pm8226', 'qcom,pm8350', 'qcom,pm8350b', 'qcom,pm8350c', 'qcom,pm8450', 'qcom,pm8550', 'qcom,pm8550b', 'qcom,pm8550ve', 'qcom,pm8550vs', 'qcom,pm8841', 'qcom,pm8909', 'qcom,pm8916', 'qcom,pm8937', 'qcom,pm8941', 'qcom,pm8950', 'qcom,pm8953', 'qcom,pm8994', 'qcom,pm8998', 'qcom,pma8084', 'qcom,pmc8180', 'qcom,pmc8180c', 'qcom,pmd9635', 'qcom,pmi632', 'qcom,pmi8950', 'qcom,pmi8962', 'qcom,pmi8994', 'qcom,pmi8998', 'qcom,pmk8002', 'qcom,pmk8350', 'qcom,pmk8550', 'qcom,pmm8155au', 'qcom,pmm8654au', 'qcom,pmp8074', 'qcom,pmr735a', 'qcom,pmr735b', 'qcom,pmr735d', 'qcom,pms405', 'qcom,pmx55', 'qcom,pmx65', 'qcom,pmx75', 'qcom,smb2351'] -- arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: phy@fda000: 'vdda-pll-supply' is a required property from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: phy@fdf000: 'vdda-phy-supply' is a required property from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: phy@fdf000: 'vdda-pll-supply' is a required property from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: gmu@3d6a000: reg-names:0: 'gmu' was expected from schema $id: http://devicetree.org/schemas/display/msm/gmu.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: gmu@3d6a000: reg-names:1: 'rscc' was expected from schema $id: http://devicetree.org/schemas/display/msm/gmu.yaml# >> arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: iommu@3da0000: compatible: 'oneOf' conditional failed, one must be fixed: ['qcom,x1e80100-smmu-500', 'qcom,adreno-smmu', 'qcom,smmu-500', 'arm,mmu-500'] is too long 'qcom,x1e80100-smmu-500' is not one of ['qcom,msm8996-smmu-v2', 'qcom,msm8998-smmu-v2', 'qcom,sdm630-smmu-v2', 'qcom,sm6375-smmu-v2'] 'qcom,x1e80100-smmu-500' is not one of ['qcom,qcm2290-smmu-500', 'qcom,sc7180-smmu-500', 'qcom,sc7280-smmu-500', 'qcom,sc8180x-smmu-500', 'qcom,sc8280xp-smmu-500', 'qcom,sdm845-smmu-500', 'qcom,sm6115-smmu-500', 'qcom,sm6350-smmu-500', 'qcom,sm6375-smmu-500', 'qcom,sm8150-smmu-500', 'qcom,sm8250-smmu-500', 'qcom,sm8350-smmu-500', 'qcom,sm8450-smmu-500'] 'qcom,x1e80100-smmu-500' is not one of ['qcom,qcm2290-smmu-500', 'qcom,sa8775p-smmu-500', 'qcom,sc7280-smmu-500', 'qcom,sc8280xp-smmu-500', 'qcom,sm6115-smmu-500', 'qcom,sm6125-smmu-500', 'qcom,sm8150-smmu-500', 'qcom,sm8250-smmu-500', 'qcom,sm8350-smmu-500', 'qcom,sm8450-smmu-500', 'qcom,sm8550-smmu-500', 'qcom,sm8650-smmu-500'] 'qcom,x1e80100-smmu-500' is not one of ['qcom,sc7280-smmu-500', 'qcom,sm8150-smmu-500', 'qcom,sm8250-smmu-500'] 'qcom,x1e80100-smmu-500' is not one of ['qcom,msm8996-smmu-v2', 'qcom,sc7180-smmu-v2', 'qcom,sdm630-smmu-v2', 'qcom,sdm845-smmu-v2', 'qcom,sm6350-smmu-v2', 'qcom,sm7150-smmu-v2'] 'qcom,sdm845-smmu-v2' was expected 'marvell,ap806-smmu-500' was expected 'qcom,x1e80100-smmu-500' is not one of ['nvidia,tegra186-smmu', 'nvidia,tegra194-smmu', 'nvidia,tegra234-smmu'] 'arm,mmu-500' was expected 'qcom,x1e80100-smmu-500' is not one of ['arm,mmu-400', 'arm,mmu-401'] 'qcom,x1e80100-smmu-500' is not one of ['arm,smmu-v1', 'arm,smmu-v2', 'arm,mmu-400', 'arm,mmu-401', 'arm,mmu-500', 'cavium,smmu-v2'] 'qcom,smmu-v2' was expected 'qcom,smmu-500' was expected 'nvidia,smmu-500' was expected 'arm,smmu-v2' was expected 'arm,smmu-v1' was expected from schema $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# >> arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: iommu@3da0000: clock-names: False schema does not allow ['hlos', 'bus', 'iface', 'ahb'] from schema $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# >> arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: iommu@3da0000: clocks: False schema does not allow [[146, 14], [51, 55], [51, 56], [146, 0]] from schema $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: usb@a2f8800: interrupt-names: ['pwr_event', 'dp_hs_phy_irq', 'dm_hs_phy_irq'] is too short from schema $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: pmic@7: compatible:0: 'qcom,smb2360' is not one of ['qcom,pm2250', 'qcom,pm6125', 'qcom,pm6150', 'qcom,pm6150l', 'qcom,pm6350', 'qcom,pm660', 'qcom,pm660l', 'qcom,pm7250b', 'qcom,pm7550ba', 'qcom,pm7325', 'qcom,pm8004', 'qcom,pm8005', 'qcom,pm8009', 'qcom,pm8010', 'qcom,pm8019', 'qcom,pm8028', 'qcom,pm8110', 'qcom,pm8150', 'qcom,pm8150b', 'qcom,pm8150c', 'qcom,pm8150l', 'qcom,pm8226', 'qcom,pm8350', 'qcom,pm8350b', 'qcom,pm8350c', 'qcom,pm8450', 'qcom,pm8550', 'qcom,pm8550b', 'qcom,pm8550ve', 'qcom,pm8550vs', 'qcom,pm8841', 'qcom,pm8909', 'qcom,pm8916', 'qcom,pm8937', 'qcom,pm8941', 'qcom,pm8950', 'qcom,pm8953', 'qcom,pm8994', 'qcom,pm8998', 'qcom,pma8084', 'qcom,pmc8180', 'qcom,pmc8180c', 'qcom,pmd9635', 'qcom,pmi632', 'qcom,pmi8950', 'qcom,pmi8962', 'qcom,pmi8994', 'qcom,pmi8998', 'qcom,pmk8002', 'qcom,pmk8350', 'qcom,pmk8550', 'qcom,pmm8155au', 'qcom,pmm8654au', 'qcom,pmp8074', 'qcom,pmr735a', 'qcom,pmr735b', 'qcom,pmr735d', 'qcom,pms405', 'qcom,pmx55', 'qcom,pmx65', 'qcom,pmx75', 'qcom,smb2351'] from schema $id: http://devicetree.org/schemas/mfd/qcom,spmi-pmic.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: /soc@0/arbiter@c400000/spmi@c432000/pmic@7: failed to match any schema with compatible: ['qcom,smb2360', 'qcom,spmi-pmic'] arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: pmic@a: compatible:0: 'qcom,smb2360' is not one of ['qcom,pm2250', 'qcom,pm6125', 'qcom,pm6150', 'qcom,pm6150l', 'qcom,pm6350', 'qcom,pm660', 'qcom,pm660l', 'qcom,pm7250b', 'qcom,pm7550ba', 'qcom,pm7325', 'qcom,pm8004', 'qcom,pm8005', 'qcom,pm8009', 'qcom,pm8010', 'qcom,pm8019', 'qcom,pm8028', 'qcom,pm8110', 'qcom,pm8150', 'qcom,pm8150b', 'qcom,pm8150c', 'qcom,pm8150l', 'qcom,pm8226', 'qcom,pm8350', 'qcom,pm8350b', 'qcom,pm8350c', 'qcom,pm8450', 'qcom,pm8550', 'qcom,pm8550b', 'qcom,pm8550ve', 'qcom,pm8550vs', 'qcom,pm8841', 'qcom,pm8909', 'qcom,pm8916', 'qcom,pm8937', 'qcom,pm8941', 'qcom,pm8950', 'qcom,pm8953', 'qcom,pm8994', 'qcom,pm8998', 'qcom,pma8084', 'qcom,pmc8180', 'qcom,pmc8180c', 'qcom,pmd9635', 'qcom,pmi632', 'qcom,pmi8950', 'qcom,pmi8962', 'qcom,pmi8994', 'qcom,pmi8998', 'qcom,pmk8002', 'qcom,pmk8350', 'qcom,pmk8550', 'qcom,pmm8155au', 'qcom,pmm8654au', 'qcom,pmp8074', 'qcom,pmr735a', 'qcom,pmr735b', 'qcom,pmr735d', 'qcom,pms405', 'qcom,pmx55', 'qcom,pmx65', 'qcom,pmx75', 'qcom,smb2351'] from schema $id: http://devicetree.org/schemas/mfd/qcom,spmi-pmic.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: /soc@0/arbiter@c400000/spmi@c432000/pmic@a: failed to match any schema with compatible: ['qcom,smb2360', 'qcom,spmi-pmic'] arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: pmic@b: compatible:0: 'qcom,smb2360' is not one of ['qcom,pm2250', 'qcom,pm6125', 'qcom,pm6150', 'qcom,pm6150l', 'qcom,pm6350', 'qcom,pm660', 'qcom,pm660l', 'qcom,pm7250b', 'qcom,pm7550ba', 'qcom,pm7325', 'qcom,pm8004', 'qcom,pm8005', 'qcom,pm8009', 'qcom,pm8010', 'qcom,pm8019', 'qcom,pm8028', 'qcom,pm8110', 'qcom,pm8150', 'qcom,pm8150b', 'qcom,pm8150c', 'qcom,pm8150l', 'qcom,pm8226', 'qcom,pm8350', 'qcom,pm8350b', 'qcom,pm8350c', 'qcom,pm8450', 'qcom,pm8550', 'qcom,pm8550b', 'qcom,pm8550ve', 'qcom,pm8550vs', 'qcom,pm8841', 'qcom,pm8909', 'qcom,pm8916', 'qcom,pm8937', 'qcom,pm8941', 'qcom,pm8950', 'qcom,pm8953', 'qcom,pm8994', 'qcom,pm8998', 'qcom,pma8084', 'qcom,pmc8180', 'qcom,pmc8180c', 'qcom,pmd9635', 'qcom,pmi632', 'qcom,pmi8950', 'qcom,pmi8962', 'qcom,pmi8994', 'qcom,pmi8998', 'qcom,pmk8002', 'qcom,pmk8350', 'qcom,pmk8550', 'qcom,pmm8155au', 'qcom,pmm8654au', 'qcom,pmp8074', 'qcom,pmr735a', 'qcom,pmr735b', 'qcom,pmr735d', 'qcom,pms405', 'qcom,pmx55', 'qcom,pmx65', 'qcom,pmx75', 'qcom,smb2351']
Hi Akhil, kernel test robot noticed the following build warnings: [auto build test WARNING on robh/for-next] [also build test WARNING on drm-intel/for-linux-next drm-intel/for-linux-next-fixes drm-tip/drm-tip linus/master v6.10-rc5] [cannot apply to next-20240628] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Akhil-P-Oommen/dt-bindings-display-msm-gmu-Add-Adreno-X185-GMU/20240626-061111 base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next patch link: https://lore.kernel.org/r/20240623110753.141400-4-quic_akhilpo%40quicinc.com patch subject: [PATCH v1 3/3] arm64: dts: qcom: x1e80100: Add gpu support config: arm64-allmodconfig compiler: clang version 19.0.0git (https://github.com/llvm/llvm-project ad79a14c9e5ec4a369eed4adf567c22cc029863f) reproduce (this is a W=1 build): If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202406291700.IprmlMGB-lkp@intel.com/ dtcheck warnings: (new ones prefixed by >>) >> arch/arm64/boot/dts/qcom/x1e80100.dtsi:3076.20-3126.5: Warning (simple_bus_reg): /soc@0/gmu@3d6a000: simple-bus unit address format error, expected "3d50000" vim +/3d50000 +3076 arch/arm64/boot/dts/qcom/x1e80100.dtsi 22 23 / { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 chosen { }; 30 31 clocks { 32 xo_board: xo-board { 33 compatible = "fixed-clock"; 34 clock-frequency = <76800000>; 35 #clock-cells = <0>; 36 }; 37 38 sleep_clk: sleep-clk { 39 compatible = "fixed-clock"; 40 clock-frequency = <32000>; 41 #clock-cells = <0>; 42 }; 43 44 bi_tcxo_div2: bi-tcxo-div2-clk { 45 compatible = "fixed-factor-clock"; 46 #clock-cells = <0>; 47 48 clocks = <&rpmhcc RPMH_CXO_CLK>; 49 clock-mult = <1>; 50 clock-div = <2>; 51 }; 52 53 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 54 compatible = "fixed-factor-clock"; 55 #clock-cells = <0>; 56 57 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 58 clock-mult = <1>; 59 clock-div = <2>; 60 }; 61 }; 62 63 cpus { 64 #address-cells = <2>; 65 #size-cells = <0>; 66 67 CPU0: cpu@0 { 68 device_type = "cpu"; 69 compatible = "qcom,oryon"; 70 reg = <0x0 0x0>; 71 enable-method = "psci"; 72 next-level-cache = <&L2_0>; 73 power-domains = <&CPU_PD0>; 74 power-domain-names = "psci"; 75 cpu-idle-states = <&CLUSTER_C4>; 76 77 L2_0: l2-cache { 78 compatible = "cache"; 79 cache-level = <2>; 80 cache-unified; 81 }; 82 }; 83 84 CPU1: cpu@100 { 85 device_type = "cpu"; 86 compatible = "qcom,oryon"; 87 reg = <0x0 0x100>; 88 enable-method = "psci"; 89 next-level-cache = <&L2_0>; 90 power-domains = <&CPU_PD1>; 91 power-domain-names = "psci"; 92 cpu-idle-states = <&CLUSTER_C4>; 93 }; 94 95 CPU2: cpu@200 { 96 device_type = "cpu"; 97 compatible = "qcom,oryon"; 98 reg = <0x0 0x200>; 99 enable-method = "psci"; 100 next-level-cache = <&L2_0>; 101 power-domains = <&CPU_PD2>; 102 power-domain-names = "psci"; 103 cpu-idle-states = <&CLUSTER_C4>; 104 }; 105 106 CPU3: cpu@300 { 107 device_type = "cpu"; 108 compatible = "qcom,oryon"; 109 reg = <0x0 0x300>; 110 enable-method = "psci"; 111 next-level-cache = <&L2_0>; 112 power-domains = <&CPU_PD3>; 113 power-domain-names = "psci"; 114 cpu-idle-states = <&CLUSTER_C4>; 115 }; 116 117 CPU4: cpu@10000 { 118 device_type = "cpu"; 119 compatible = "qcom,oryon"; 120 reg = <0x0 0x10000>; 121 enable-method = "psci"; 122 next-level-cache = <&L2_1>; 123 power-domains = <&CPU_PD4>; 124 power-domain-names = "psci"; 125 cpu-idle-states = <&CLUSTER_C4>; 126 127 L2_1: l2-cache { 128 compatible = "cache"; 129 cache-level = <2>; 130 cache-unified; 131 }; 132 }; 133 134 CPU5: cpu@10100 { 135 device_type = "cpu"; 136 compatible = "qcom,oryon"; 137 reg = <0x0 0x10100>; 138 enable-method = "psci"; 139 next-level-cache = <&L2_1>; 140 power-domains = <&CPU_PD5>; 141 power-domain-names = "psci"; 142 cpu-idle-states = <&CLUSTER_C4>; 143 }; 144 145 CPU6: cpu@10200 { 146 device_type = "cpu"; 147 compatible = "qcom,oryon"; 148 reg = <0x0 0x10200>; 149 enable-method = "psci"; 150 next-level-cache = <&L2_1>; 151 power-domains = <&CPU_PD6>; 152 power-domain-names = "psci"; 153 cpu-idle-states = <&CLUSTER_C4>; 154 }; 155 156 CPU7: cpu@10300 { 157 device_type = "cpu"; 158 compatible = "qcom,oryon"; 159 reg = <0x0 0x10300>; 160 enable-method = "psci"; 161 next-level-cache = <&L2_1>; 162 power-domains = <&CPU_PD7>; 163 power-domain-names = "psci"; 164 cpu-idle-states = <&CLUSTER_C4>; 165 }; 166 167 CPU8: cpu@20000 { 168 device_type = "cpu"; 169 compatible = "qcom,oryon"; 170 reg = <0x0 0x20000>; 171 enable-method = "psci"; 172 next-level-cache = <&L2_2>; 173 power-domains = <&CPU_PD8>; 174 power-domain-names = "psci"; 175 cpu-idle-states = <&CLUSTER_C4>; 176 177 L2_2: l2-cache { 178 compatible = "cache"; 179 cache-level = <2>; 180 cache-unified; 181 }; 182 }; 183 184 CPU9: cpu@20100 { 185 device_type = "cpu"; 186 compatible = "qcom,oryon"; 187 reg = <0x0 0x20100>; 188 enable-method = "psci"; 189 next-level-cache = <&L2_2>; 190 power-domains = <&CPU_PD9>; 191 power-domain-names = "psci"; 192 cpu-idle-states = <&CLUSTER_C4>; 193 }; 194 195 CPU10: cpu@20200 { 196 device_type = "cpu"; 197 compatible = "qcom,oryon"; 198 reg = <0x0 0x20200>; 199 enable-method = "psci"; 200 next-level-cache = <&L2_2>; 201 power-domains = <&CPU_PD10>; 202 power-domain-names = "psci"; 203 cpu-idle-states = <&CLUSTER_C4>; 204 }; 205 206 CPU11: cpu@20300 { 207 device_type = "cpu"; 208 compatible = "qcom,oryon"; 209 reg = <0x0 0x20300>; 210 enable-method = "psci"; 211 next-level-cache = <&L2_2>; 212 power-domains = <&CPU_PD11>; 213 power-domain-names = "psci"; 214 cpu-idle-states = <&CLUSTER_C4>; 215 }; 216 217 cpu-map { 218 cluster0 { 219 core0 { 220 cpu = <&CPU0>; 221 }; 222 223 core1 { 224 cpu = <&CPU1>; 225 }; 226 227 core2 { 228 cpu = <&CPU2>; 229 }; 230 231 core3 { 232 cpu = <&CPU3>; 233 }; 234 }; 235 236 cluster1 { 237 core0 { 238 cpu = <&CPU4>; 239 }; 240 241 core1 { 242 cpu = <&CPU5>; 243 }; 244 245 core2 { 246 cpu = <&CPU6>; 247 }; 248 249 core3 { 250 cpu = <&CPU7>; 251 }; 252 }; 253 254 cluster2 { 255 core0 { 256 cpu = <&CPU8>; 257 }; 258 259 core1 { 260 cpu = <&CPU9>; 261 }; 262 263 core2 { 264 cpu = <&CPU10>; 265 }; 266 267 core3 { 268 cpu = <&CPU11>; 269 }; 270 }; 271 }; 272 273 idle-states { 274 entry-method = "psci"; 275 276 CLUSTER_C4: cpu-sleep-0 { 277 compatible = "arm,idle-state"; 278 idle-state-name = "ret"; 279 arm,psci-suspend-param = <0x00000004>; 280 entry-latency-us = <180>; 281 exit-latency-us = <320>; 282 min-residency-us = <1000>; 283 }; 284 }; 285 286 domain-idle-states { 287 CLUSTER_CL4: cluster-sleep-0 { 288 compatible = "domain-idle-state"; 289 idle-state-name = "l2-ret"; 290 arm,psci-suspend-param = <0x01000044>; 291 entry-latency-us = <350>; 292 exit-latency-us = <500>; 293 min-residency-us = <2500>; 294 }; 295 296 CLUSTER_CL5: cluster-sleep-1 { 297 compatible = "domain-idle-state"; 298 idle-state-name = "ret-pll-off"; 299 arm,psci-suspend-param = <0x01000054>; 300 entry-latency-us = <2200>; 301 exit-latency-us = <2500>; 302 min-residency-us = <7000>; 303 }; 304 }; 305 }; 306 307 firmware { 308 scm: scm { 309 compatible = "qcom,scm-x1e80100", "qcom,scm"; 310 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 311 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 312 }; 313 }; 314 315 clk_virt: interconnect-0 { 316 compatible = "qcom,x1e80100-clk-virt"; 317 #interconnect-cells = <2>; 318 qcom,bcm-voters = <&apps_bcm_voter>; 319 }; 320 321 mc_virt: interconnect-1 { 322 compatible = "qcom,x1e80100-mc-virt"; 323 #interconnect-cells = <2>; 324 qcom,bcm-voters = <&apps_bcm_voter>; 325 }; 326 327 memory@80000000 { 328 device_type = "memory"; 329 /* We expect the bootloader to fill in the size */ 330 reg = <0 0x80000000 0 0>; 331 }; 332 333 pmu { 334 compatible = "arm,armv8-pmuv3"; 335 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 336 }; 337 338 psci { 339 compatible = "arm,psci-1.0"; 340 method = "smc"; 341 342 CPU_PD0: power-domain-cpu0 { 343 #power-domain-cells = <0>; 344 power-domains = <&CLUSTER_PD0>; 345 }; 346 347 CPU_PD1: power-domain-cpu1 { 348 #power-domain-cells = <0>; 349 power-domains = <&CLUSTER_PD0>; 350 }; 351 352 CPU_PD2: power-domain-cpu2 { 353 #power-domain-cells = <0>; 354 power-domains = <&CLUSTER_PD0>; 355 }; 356 357 CPU_PD3: power-domain-cpu3 { 358 #power-domain-cells = <0>; 359 power-domains = <&CLUSTER_PD0>; 360 }; 361 362 CPU_PD4: power-domain-cpu4 { 363 #power-domain-cells = <0>; 364 power-domains = <&CLUSTER_PD1>; 365 }; 366 367 CPU_PD5: power-domain-cpu5 { 368 #power-domain-cells = <0>; 369 power-domains = <&CLUSTER_PD1>; 370 }; 371 372 CPU_PD6: power-domain-cpu6 { 373 #power-domain-cells = <0>; 374 power-domains = <&CLUSTER_PD1>; 375 }; 376 377 CPU_PD7: power-domain-cpu7 { 378 #power-domain-cells = <0>; 379 power-domains = <&CLUSTER_PD1>; 380 }; 381 382 CPU_PD8: power-domain-cpu8 { 383 #power-domain-cells = <0>; 384 power-domains = <&CLUSTER_PD2>; 385 }; 386 387 CPU_PD9: power-domain-cpu9 { 388 #power-domain-cells = <0>; 389 power-domains = <&CLUSTER_PD2>; 390 }; 391 392 CPU_PD10: power-domain-cpu10 { 393 #power-domain-cells = <0>; 394 power-domains = <&CLUSTER_PD2>; 395 }; 396 397 CPU_PD11: power-domain-cpu11 { 398 #power-domain-cells = <0>; 399 power-domains = <&CLUSTER_PD2>; 400 }; 401 402 CLUSTER_PD0: power-domain-cpu-cluster0 { 403 #power-domain-cells = <0>; 404 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>; 405 power-domains = <&SYSTEM_PD>; 406 }; 407 408 CLUSTER_PD1: power-domain-cpu-cluster1 { 409 #power-domain-cells = <0>; 410 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>; 411 power-domains = <&SYSTEM_PD>; 412 }; 413 414 CLUSTER_PD2: power-domain-cpu-cluster2 { 415 #power-domain-cells = <0>; 416 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>; 417 power-domains = <&SYSTEM_PD>; 418 }; 419 420 SYSTEM_PD: power-domain-system { 421 #power-domain-cells = <0>; 422 /* TODO: system-wide idle states */ 423 }; 424 }; 425 426 reserved-memory { 427 #address-cells = <2>; 428 #size-cells = <2>; 429 ranges; 430 431 gunyah_hyp_mem: gunyah-hyp@80000000 { 432 reg = <0x0 0x80000000 0x0 0x800000>; 433 no-map; 434 }; 435 436 hyp_elf_package_mem: hyp-elf-package@80800000 { 437 reg = <0x0 0x80800000 0x0 0x200000>; 438 no-map; 439 }; 440 441 ncc_mem: ncc@80a00000 { 442 reg = <0x0 0x80a00000 0x0 0x400000>; 443 no-map; 444 }; 445 446 cpucp_log_mem: cpucp-log@80e00000 { 447 reg = <0x0 0x80e00000 0x0 0x40000>; 448 no-map; 449 }; 450 451 cpucp_mem: cpucp@80e40000 { 452 reg = <0x0 0x80e40000 0x0 0x540000>; 453 no-map; 454 }; 455 456 reserved-region@81380000 { 457 reg = <0x0 0x81380000 0x0 0x80000>; 458 no-map; 459 }; 460 461 tags_mem: tags-region@81400000 { 462 reg = <0x0 0x81400000 0x0 0x1a0000>; 463 no-map; 464 }; 465 466 xbl_dtlog_mem: xbl-dtlog@81a00000 { 467 reg = <0x0 0x81a00000 0x0 0x40000>; 468 no-map; 469 }; 470 471 xbl_ramdump_mem: xbl-ramdump@81a40000 { 472 reg = <0x0 0x81a40000 0x0 0x1c0000>; 473 no-map; 474 }; 475 476 aop_image_mem: aop-image@81c00000 { 477 reg = <0x0 0x81c00000 0x0 0x60000>; 478 no-map; 479 }; 480 481 aop_cmd_db_mem: aop-cmd-db@81c60000 { 482 compatible = "qcom,cmd-db"; 483 reg = <0x0 0x81c60000 0x0 0x20000>; 484 no-map; 485 }; 486 487 aop_config_mem: aop-config@81c80000 { 488 reg = <0x0 0x81c80000 0x0 0x20000>; 489 no-map; 490 }; 491 492 tme_crash_dump_mem: tme-crash-dump@81ca0000 { 493 reg = <0x0 0x81ca0000 0x0 0x40000>; 494 no-map; 495 }; 496 497 tme_log_mem: tme-log@81ce0000 { 498 reg = <0x0 0x81ce0000 0x0 0x4000>; 499 no-map; 500 }; 501 502 uefi_log_mem: uefi-log@81ce4000 { 503 reg = <0x0 0x81ce4000 0x0 0x10000>; 504 no-map; 505 }; 506 507 secdata_apss_mem: secdata-apss@81cff000 { 508 reg = <0x0 0x81cff000 0x0 0x1000>; 509 no-map; 510 }; 511 512 pdp_ns_shared_mem: pdp-ns-shared@81e00000 { 513 reg = <0x0 0x81e00000 0x0 0x100000>; 514 no-map; 515 }; 516 517 gpu_prr_mem: gpu-prr@81f00000 { 518 reg = <0x0 0x81f00000 0x0 0x10000>; 519 no-map; 520 }; 521 522 tpm_control_mem: tpm-control@81f10000 { 523 reg = <0x0 0x81f10000 0x0 0x10000>; 524 no-map; 525 }; 526 527 usb_ucsi_shared_mem: usb-ucsi-shared@81f20000 { 528 reg = <0x0 0x81f20000 0x0 0x10000>; 529 no-map; 530 }; 531 532 pld_pep_mem: pld-pep@81f30000 { 533 reg = <0x0 0x81f30000 0x0 0x6000>; 534 no-map; 535 }; 536 537 pld_gmu_mem: pld-gmu@81f36000 { 538 reg = <0x0 0x81f36000 0x0 0x1000>; 539 no-map; 540 }; 541 542 pld_pdp_mem: pld-pdp@81f37000 { 543 reg = <0x0 0x81f37000 0x0 0x1000>; 544 no-map; 545 }; 546 547 tz_stat_mem: tz-stat@82700000 { 548 reg = <0x0 0x82700000 0x0 0x100000>; 549 no-map; 550 }; 551 552 xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 { 553 reg = <0x0 0x82800000 0x0 0xc00000>; 554 no-map; 555 }; 556 557 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 { 558 reg = <0x0 0x84b00000 0x0 0x800000>; 559 no-map; 560 }; 561 562 spu_secure_shared_memory_mem: spu-secure-shared-memory@85300000 { 563 reg = <0x0 0x85300000 0x0 0x80000>; 564 no-map; 565 }; 566 567 adsp_boot_dtb_mem: adsp-boot-dtb@866c0000 { 568 reg = <0x0 0x866c0000 0x0 0x40000>; 569 no-map; 570 }; 571 572 spss_region_mem: spss-region@86700000 { 573 reg = <0x0 0x86700000 0x0 0x400000>; 574 no-map; 575 }; 576 577 adsp_boot_mem: adsp-boot@86b00000 { 578 reg = <0x0 0x86b00000 0x0 0xc00000>; 579 no-map; 580 }; 581 582 video_mem: video@87700000 { 583 reg = <0x0 0x87700000 0x0 0x700000>; 584 no-map; 585 }; 586 587 adspslpi_mem: adspslpi@87e00000 { 588 reg = <0x0 0x87e00000 0x0 0x3a00000>; 589 no-map; 590 }; 591 592 q6_adsp_dtb_mem: q6-adsp-dtb@8b800000 { 593 reg = <0x0 0x8b800000 0x0 0x80000>; 594 no-map; 595 }; 596 597 cdsp_mem: cdsp@8b900000 { 598 reg = <0x0 0x8b900000 0x0 0x2000000>; 599 no-map; 600 }; 601 602 q6_cdsp_dtb_mem: q6-cdsp-dtb@8d900000 { 603 reg = <0x0 0x8d900000 0x0 0x80000>; 604 no-map; 605 }; 606 607 gpu_microcode_mem: gpu-microcode@8d9fe000 { 608 reg = <0x0 0x8d9fe000 0x0 0x2000>; 609 no-map; 610 }; 611 612 cvp_mem: cvp@8da00000 { 613 reg = <0x0 0x8da00000 0x0 0x700000>; 614 no-map; 615 }; 616 617 camera_mem: camera@8e100000 { 618 reg = <0x0 0x8e100000 0x0 0x800000>; 619 no-map; 620 }; 621 622 av1_encoder_mem: av1-encoder@8e900000 { 623 reg = <0x0 0x8e900000 0x0 0x700000>; 624 no-map; 625 }; 626 627 reserved-region@8f000000 { 628 reg = <0x0 0x8f000000 0x0 0xa00000>; 629 no-map; 630 }; 631 632 wpss_mem: wpss@8fa00000 { 633 reg = <0x0 0x8fa00000 0x0 0x1900000>; 634 no-map; 635 }; 636 637 q6_wpss_dtb_mem: q6-wpss-dtb@91300000 { 638 reg = <0x0 0x91300000 0x0 0x80000>; 639 no-map; 640 }; 641 642 xbl_sc_mem: xbl-sc@d8000000 { 643 reg = <0x0 0xd8000000 0x0 0x40000>; 644 no-map; 645 }; 646 647 reserved-region@d8040000 { 648 reg = <0x0 0xd8040000 0x0 0xa0000>; 649 no-map; 650 }; 651 652 qtee_mem: qtee@d80e0000 { 653 reg = <0x0 0xd80e0000 0x0 0x520000>; 654 no-map; 655 }; 656 657 ta_mem: ta@d8600000 { 658 reg = <0x0 0xd8600000 0x0 0x8a00000>; 659 no-map; 660 }; 661 662 tags_mem1: tags@e1000000 { 663 reg = <0x0 0xe1000000 0x0 0x26a0000>; 664 no-map; 665 }; 666 667 llcc_lpi_mem: llcc-lpi@ff800000 { 668 reg = <0x0 0xff800000 0x0 0x600000>; 669 no-map; 670 }; 671 672 smem_mem: smem@ffe00000 { 673 compatible = "qcom,smem"; 674 reg = <0x0 0xffe00000 0x0 0x200000>; 675 hwlocks = <&tcsr_mutex 3>; 676 no-map; 677 }; 678 }; 679 680 smp2p-adsp { 681 compatible = "qcom,smp2p"; 682 683 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 684 IPCC_MPROC_SIGNAL_SMP2P 685 IRQ_TYPE_EDGE_RISING>; 686 687 mboxes = <&ipcc IPCC_CLIENT_LPASS 688 IPCC_MPROC_SIGNAL_SMP2P>; 689 690 qcom,smem = <443>, <429>; 691 qcom,local-pid = <0>; 692 qcom,remote-pid = <2>; 693 694 smp2p_adsp_out: master-kernel { 695 qcom,entry-name = "master-kernel"; 696 #qcom,smem-state-cells = <1>; 697 }; 698 699 smp2p_adsp_in: slave-kernel { 700 qcom,entry-name = "slave-kernel"; 701 interrupt-controller; 702 #interrupt-cells = <2>; 703 }; 704 }; 705 706 smp2p-cdsp { 707 compatible = "qcom,smp2p"; 708 709 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 710 IPCC_MPROC_SIGNAL_SMP2P 711 IRQ_TYPE_EDGE_RISING>; 712 713 mboxes = <&ipcc IPCC_CLIENT_CDSP 714 IPCC_MPROC_SIGNAL_SMP2P>; 715 716 qcom,smem = <94>, <432>; 717 qcom,local-pid = <0>; 718 qcom,remote-pid = <5>; 719 720 smp2p_cdsp_out: master-kernel { 721 qcom,entry-name = "master-kernel"; 722 #qcom,smem-state-cells = <1>; 723 }; 724 725 smp2p_cdsp_in: slave-kernel { 726 qcom,entry-name = "slave-kernel"; 727 interrupt-controller; 728 #interrupt-cells = <2>; 729 }; 730 }; 731 732 soc: soc@0 { 733 compatible = "simple-bus"; 734 735 #address-cells = <2>; 736 #size-cells = <2>; 737 dma-ranges = <0 0 0 0 0x10 0>; 738 ranges = <0 0 0 0 0x10 0>; 739 740 gcc: clock-controller@100000 { 741 compatible = "qcom,x1e80100-gcc"; 742 reg = <0 0x00100000 0 0x200000>; 743 744 clocks = <&bi_tcxo_div2>, 745 <&sleep_clk>, 746 <0>, 747 <&pcie4_phy>, 748 <0>, 749 <&pcie6a_phy>, 750 <0>, 751 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 752 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 753 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 754 755 power-domains = <&rpmhpd RPMHPD_CX>; 756 #clock-cells = <1>; 757 #reset-cells = <1>; 758 #power-domain-cells = <1>; 759 }; 760 761 ipcc: mailbox@408000 { 762 compatible = "qcom,x1e80100-ipcc", "qcom,ipcc"; 763 reg = <0 0x00408000 0 0x1000>; 764 765 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 766 interrupt-controller; 767 #interrupt-cells = <3>; 768 769 #mbox-cells = <2>; 770 }; 771 772 gpi_dma2: dma-controller@800000 { 773 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 774 reg = <0 0x00800000 0 0x60000>; 775 776 interrupts = <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>; 788 789 dma-channels = <12>; 790 dma-channel-mask = <0x3e>; 791 #dma-cells = <3>; 792 793 iommus = <&apps_smmu 0x436 0x0>; 794 795 status = "disabled"; 796 }; 797 798 qupv3_2: geniqup@8c0000 { 799 compatible = "qcom,geni-se-qup"; 800 reg = <0 0x008c0000 0 0x2000>; 801 802 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 803 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 804 clock-names = "m-ahb", 805 "s-ahb"; 806 807 iommus = <&apps_smmu 0x423 0x0>; 808 809 #address-cells = <2>; 810 #size-cells = <2>; 811 ranges; 812 813 status = "disabled"; 814 815 i2c16: i2c@880000 { 816 compatible = "qcom,geni-i2c"; 817 reg = <0 0x00880000 0 0x4000>; 818 819 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>; 820 821 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 822 clock-names = "se"; 823 824 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 825 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 826 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 827 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 828 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 829 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 830 interconnect-names = "qup-core", 831 "qup-config", 832 "qup-memory"; 833 834 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 835 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 836 dma-names = "tx", 837 "rx"; 838 839 pinctrl-0 = <&qup_i2c16_data_clk>; 840 pinctrl-names = "default"; 841 842 #address-cells = <1>; 843 #size-cells = <0>; 844 845 status = "disabled"; 846 }; 847 848 spi16: spi@880000 { 849 compatible = "qcom,geni-spi"; 850 reg = <0 0x00880000 0 0x4000>; 851 852 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>; 853 854 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 855 clock-names = "se"; 856 857 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 858 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 859 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 860 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 861 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 862 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 863 interconnect-names = "qup-core", 864 "qup-config", 865 "qup-memory"; 866 867 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 868 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 869 dma-names = "tx", 870 "rx"; 871 872 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 873 pinctrl-names = "default"; 874 875 #address-cells = <1>; 876 #size-cells = <0>; 877 878 status = "disabled"; 879 }; 880 881 i2c17: i2c@884000 { 882 compatible = "qcom,geni-i2c"; 883 reg = <0 0x00884000 0 0x4000>; 884 885 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>; 886 887 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 888 clock-names = "se"; 889 890 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 891 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 892 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 893 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 894 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 895 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 896 interconnect-names = "qup-core", 897 "qup-config", 898 "qup-memory"; 899 900 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 901 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 902 dma-names = "tx", 903 "rx"; 904 905 pinctrl-0 = <&qup_i2c17_data_clk>; 906 pinctrl-names = "default"; 907 908 #address-cells = <1>; 909 #size-cells = <0>; 910 911 status = "disabled"; 912 }; 913 914 spi17: spi@884000 { 915 compatible = "qcom,geni-spi"; 916 reg = <0 0x00884000 0 0x4000>; 917 918 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>; 919 920 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 921 clock-names = "se"; 922 923 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 924 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 925 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 926 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 927 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 928 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 929 interconnect-names = "qup-core", 930 "qup-config", 931 "qup-memory"; 932 933 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 934 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 935 dma-names = "tx", 936 "rx"; 937 938 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 939 pinctrl-names = "default"; 940 941 #address-cells = <1>; 942 #size-cells = <0>; 943 944 status = "disabled"; 945 }; 946 947 i2c18: i2c@888000 { 948 compatible = "qcom,geni-i2c"; 949 reg = <0 0x00888000 0 0x4000>; 950 951 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 952 953 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 954 clock-names = "se"; 955 956 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 957 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 958 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 959 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 960 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 961 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 962 interconnect-names = "qup-core", 963 "qup-config", 964 "qup-memory"; 965 966 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 967 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 968 dma-names = "tx", 969 "rx"; 970 971 pinctrl-0 = <&qup_i2c18_data_clk>; 972 pinctrl-names = "default"; 973 974 #address-cells = <1>; 975 #size-cells = <0>; 976 977 status = "disabled"; 978 }; 979 980 spi18: spi@888000 { 981 compatible = "qcom,geni-spi"; 982 reg = <0 0x00888000 0 0x4000>; 983 984 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 985 986 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 987 clock-names = "se"; 988 989 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 990 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 991 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 992 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 993 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 994 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 995 interconnect-names = "qup-core", 996 "qup-config", 997 "qup-memory"; 998 999 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1000 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1001 dma-names = "tx", 1002 "rx"; 1003 1004 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 1005 pinctrl-names = "default"; 1006 1007 #address-cells = <1>; 1008 #size-cells = <0>; 1009 1010 status = "disabled"; 1011 }; 1012 1013 i2c19: i2c@88c000 { 1014 compatible = "qcom,geni-i2c"; 1015 reg = <0 0x0088c000 0 0x4000>; 1016 1017 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>; 1018 1019 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1020 clock-names = "se"; 1021 1022 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1023 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1024 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1025 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1026 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1027 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1028 interconnect-names = "qup-core", 1029 "qup-config", 1030 "qup-memory"; 1031 1032 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1033 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1034 dma-names = "tx", 1035 "rx"; 1036 1037 pinctrl-0 = <&qup_i2c19_data_clk>; 1038 pinctrl-names = "default"; 1039 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 1043 status = "disabled"; 1044 }; 1045 1046 spi19: spi@88c000 { 1047 compatible = "qcom,geni-spi"; 1048 reg = <0 0x0088c000 0 0x4000>; 1049 1050 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>; 1051 1052 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1053 clock-names = "se"; 1054 1055 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1056 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1057 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1058 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1059 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1060 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1061 interconnect-names = "qup-core", 1062 "qup-config", 1063 "qup-memory"; 1064 1065 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1066 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1067 dma-names = "tx", 1068 "rx"; 1069 1070 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 1071 pinctrl-names = "default"; 1072 1073 #address-cells = <1>; 1074 #size-cells = <0>; 1075 1076 status = "disabled"; 1077 }; 1078 1079 i2c20: i2c@890000 { 1080 compatible = "qcom,geni-i2c"; 1081 reg = <0 0x00890000 0 0x4000>; 1082 1083 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>; 1084 1085 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1086 clock-names = "se"; 1087 1088 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1089 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1090 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1091 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1092 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1093 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1094 interconnect-names = "qup-core", 1095 "qup-config", 1096 "qup-memory"; 1097 1098 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1099 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1100 dma-names = "tx", 1101 "rx"; 1102 1103 pinctrl-0 = <&qup_i2c20_data_clk>; 1104 pinctrl-names = "default"; 1105 1106 #address-cells = <1>; 1107 #size-cells = <0>; 1108 1109 status = "disabled"; 1110 }; 1111 1112 spi20: spi@890000 { 1113 compatible = "qcom,geni-spi"; 1114 reg = <0 0x00890000 0 0x4000>; 1115 1116 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>; 1117 1118 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1119 clock-names = "se"; 1120 1121 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1122 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1123 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1124 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1125 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1126 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1127 interconnect-names = "qup-core", 1128 "qup-config", 1129 "qup-memory"; 1130 1131 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1132 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1133 dma-names = "tx", 1134 "rx"; 1135 1136 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1137 pinctrl-names = "default"; 1138 1139 #address-cells = <1>; 1140 #size-cells = <0>; 1141 1142 status = "disabled"; 1143 }; 1144 1145 i2c21: i2c@894000 { 1146 compatible = "qcom,geni-i2c"; 1147 reg = <0 0x00894000 0 0x4000>; 1148 1149 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1150 1151 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1152 clock-names = "se"; 1153 1154 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1155 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1156 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1157 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1158 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1159 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1160 interconnect-names = "qup-core", 1161 "qup-config", 1162 "qup-memory"; 1163 1164 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1165 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1166 dma-names = "tx", 1167 "rx"; 1168 1169 pinctrl-0 = <&qup_i2c21_data_clk>; 1170 pinctrl-names = "default"; 1171 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 1175 status = "disabled"; 1176 }; 1177 1178 spi21: spi@894000 { 1179 compatible = "qcom,geni-spi"; 1180 reg = <0 0x00894000 0 0x4000>; 1181 1182 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1183 1184 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1185 clock-names = "se"; 1186 1187 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1188 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1189 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1190 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1191 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1192 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1193 interconnect-names = "qup-core", 1194 "qup-config", 1195 "qup-memory"; 1196 1197 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1198 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1199 dma-names = "tx", 1200 "rx"; 1201 1202 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1203 pinctrl-names = "default"; 1204 1205 #address-cells = <1>; 1206 #size-cells = <0>; 1207 1208 status = "disabled"; 1209 }; 1210 1211 uart21: serial@894000 { 1212 compatible = "qcom,geni-uart"; 1213 reg = <0 0x00894000 0 0x4000>; 1214 1215 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1216 1217 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1218 clock-names = "se"; 1219 1220 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1221 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1222 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1223 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1224 interconnect-names = "qup-core", 1225 "qup-config"; 1226 1227 pinctrl-0 = <&qup_uart21_default>; 1228 pinctrl-names = "default"; 1229 1230 status = "disabled"; 1231 }; 1232 1233 i2c22: i2c@898000 { 1234 compatible = "qcom,geni-i2c"; 1235 reg = <0 0x00898000 0 0x4000>; 1236 1237 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1238 1239 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1240 clock-names = "se"; 1241 1242 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1243 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1244 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1245 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1246 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1247 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1248 interconnect-names = "qup-core", 1249 "qup-config", 1250 "qup-memory"; 1251 1252 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1253 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1254 dma-names = "tx", 1255 "rx"; 1256 1257 pinctrl-0 = <&qup_i2c22_data_clk>; 1258 pinctrl-names = "default"; 1259 1260 #address-cells = <1>; 1261 #size-cells = <0>; 1262 1263 status = "disabled"; 1264 }; 1265 1266 spi22: spi@898000 { 1267 compatible = "qcom,geni-spi"; 1268 reg = <0 0x00898000 0 0x4000>; 1269 1270 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1271 1272 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1273 clock-names = "se"; 1274 1275 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1276 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1277 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1278 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1279 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1280 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1281 interconnect-names = "qup-core", 1282 "qup-config", 1283 "qup-memory"; 1284 1285 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1286 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1287 dma-names = "tx", 1288 "rx"; 1289 1290 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>; 1291 pinctrl-names = "default"; 1292 1293 #address-cells = <1>; 1294 #size-cells = <0>; 1295 1296 status = "disabled"; 1297 }; 1298 1299 i2c23: i2c@89c000 { 1300 compatible = "qcom,geni-i2c"; 1301 reg = <0 0x0089c000 0 0x4000>; 1302 1303 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1304 1305 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1306 clock-names = "se"; 1307 1308 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1309 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1310 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1311 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1312 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1313 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1314 interconnect-names = "qup-core", 1315 "qup-config", 1316 "qup-memory"; 1317 1318 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1319 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1320 dma-names = "tx", 1321 "rx"; 1322 1323 pinctrl-0 = <&qup_i2c23_data_clk>; 1324 pinctrl-names = "default"; 1325 1326 #address-cells = <1>; 1327 #size-cells = <0>; 1328 1329 status = "disabled"; 1330 }; 1331 1332 spi23: spi@89c000 { 1333 compatible = "qcom,geni-spi"; 1334 reg = <0 0x0089c000 0 0x4000>; 1335 1336 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1337 1338 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1339 clock-names = "se"; 1340 1341 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1342 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1343 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1344 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1345 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1346 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1347 interconnect-names = "qup-core", 1348 "qup-config", 1349 "qup-memory"; 1350 1351 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1352 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1353 dma-names = "tx", 1354 "rx"; 1355 1356 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>; 1357 pinctrl-names = "default"; 1358 1359 #address-cells = <1>; 1360 #size-cells = <0>; 1361 1362 status = "disabled"; 1363 }; 1364 }; 1365 1366 gpi_dma1: dma-controller@a00000 { 1367 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 1368 reg = <0 0x00a00000 0 0x60000>; 1369 1370 interrupts = <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>, 1371 <GIC_SPI 777 IRQ_TYPE_LEVEL_HIGH>, 1372 <GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>, 1373 <GIC_SPI 779 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 1375 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 1376 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 1377 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>; 1382 1383 dma-channels = <12>; 1384 dma-channel-mask = <0x3e>; 1385 #dma-cells = <3>; 1386 1387 iommus = <&apps_smmu 0x136 0x0>; 1388 1389 status = "disabled"; 1390 }; 1391 1392 qupv3_1: geniqup@ac0000 { 1393 compatible = "qcom,geni-se-qup"; 1394 reg = <0 0x00ac0000 0 0x2000>; 1395 1396 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1397 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1398 clock-names = "m-ahb", 1399 "s-ahb"; 1400 1401 iommus = <&apps_smmu 0x123 0x0>; 1402 1403 #address-cells = <2>; 1404 #size-cells = <2>; 1405 ranges; 1406 1407 status = "disabled"; 1408 1409 i2c8: i2c@a80000 { 1410 compatible = "qcom,geni-i2c"; 1411 reg = <0 0x00a80000 0 0x4000>; 1412 1413 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>; 1414 1415 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1416 clock-names = "se"; 1417 1418 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1419 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1420 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1421 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1422 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1423 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1424 interconnect-names = "qup-core", 1425 "qup-config", 1426 "qup-memory"; 1427 1428 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1429 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1430 dma-names = "tx", 1431 "rx"; 1432 1433 pinctrl-0 = <&qup_i2c8_data_clk>; 1434 pinctrl-names = "default"; 1435 1436 #address-cells = <1>; 1437 #size-cells = <0>; 1438 1439 status = "disabled"; 1440 }; 1441 1442 spi8: spi@a80000 { 1443 compatible = "qcom,geni-spi"; 1444 reg = <0 0x00a80000 0 0x4000>; 1445 1446 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>; 1447 1448 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1449 clock-names = "se"; 1450 1451 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1452 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1453 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1454 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1455 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1456 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1457 interconnect-names = "qup-core", 1458 "qup-config", 1459 "qup-memory"; 1460 1461 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1462 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1463 dma-names = "tx", 1464 "rx"; 1465 1466 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1467 pinctrl-names = "default"; 1468 1469 #address-cells = <1>; 1470 #size-cells = <0>; 1471 1472 status = "disabled"; 1473 }; 1474 1475 i2c9: i2c@a84000 { 1476 compatible = "qcom,geni-i2c"; 1477 reg = <0 0x00a84000 0 0x4000>; 1478 1479 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>; 1480 1481 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1482 clock-names = "se"; 1483 1484 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1485 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1486 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1487 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1488 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1489 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1490 interconnect-names = "qup-core", 1491 "qup-config", 1492 "qup-memory"; 1493 1494 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1495 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1496 dma-names = "tx", 1497 "rx"; 1498 1499 pinctrl-0 = <&qup_i2c9_data_clk>; 1500 pinctrl-names = "default"; 1501 1502 #address-cells = <1>; 1503 #size-cells = <0>; 1504 1505 status = "disabled"; 1506 }; 1507 1508 spi9: spi@a84000 { 1509 compatible = "qcom,geni-spi"; 1510 reg = <0 0x00a84000 0 0x4000>; 1511 1512 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>; 1513 1514 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1515 clock-names = "se"; 1516 1517 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1518 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1519 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1520 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1521 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1522 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1523 interconnect-names = "qup-core", 1524 "qup-config", 1525 "qup-memory"; 1526 1527 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1528 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1529 dma-names = "tx", 1530 "rx"; 1531 1532 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1533 pinctrl-names = "default"; 1534 1535 #address-cells = <1>; 1536 #size-cells = <0>; 1537 1538 status = "disabled"; 1539 }; 1540 1541 i2c10: i2c@a88000 { 1542 compatible = "qcom,geni-i2c"; 1543 reg = <0 0x00a88000 0 0x4000>; 1544 1545 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>; 1546 1547 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1548 clock-names = "se"; 1549 1550 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1551 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1552 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1553 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1554 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1555 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1556 interconnect-names = "qup-core", 1557 "qup-config", 1558 "qup-memory"; 1559 1560 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1561 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1562 dma-names = "tx", 1563 "rx"; 1564 1565 pinctrl-0 = <&qup_i2c10_data_clk>; 1566 pinctrl-names = "default"; 1567 1568 #address-cells = <1>; 1569 #size-cells = <0>; 1570 1571 status = "disabled"; 1572 }; 1573 1574 spi10: spi@a88000 { 1575 compatible = "qcom,geni-spi"; 1576 reg = <0 0x00a88000 0 0x4000>; 1577 1578 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>; 1579 1580 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1581 clock-names = "se"; 1582 1583 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1584 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1585 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1586 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1587 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1588 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1589 interconnect-names = "qup-core", 1590 "qup-config", 1591 "qup-memory"; 1592 1593 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1594 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1595 dma-names = "tx", 1596 "rx"; 1597 1598 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1599 pinctrl-names = "default"; 1600 1601 #address-cells = <1>; 1602 #size-cells = <0>; 1603 1604 status = "disabled"; 1605 }; 1606 1607 i2c11: i2c@a8c000 { 1608 compatible = "qcom,geni-i2c"; 1609 reg = <0 0x00a8c000 0 0x4000>; 1610 1611 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 1612 1613 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1614 clock-names = "se"; 1615 1616 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1617 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1618 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1619 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1620 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1621 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1622 interconnect-names = "qup-core", 1623 "qup-config", 1624 "qup-memory"; 1625 1626 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1627 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1628 dma-names = "tx", 1629 "rx"; 1630 1631 pinctrl-0 = <&qup_i2c11_data_clk>; 1632 pinctrl-names = "default"; 1633 1634 #address-cells = <1>; 1635 #size-cells = <0>; 1636 1637 status = "disabled"; 1638 }; 1639 1640 spi11: spi@a8c000 { 1641 compatible = "qcom,geni-spi"; 1642 reg = <0 0x00a8c000 0 0x4000>; 1643 1644 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 1645 1646 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1647 clock-names = "se"; 1648 1649 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1650 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1651 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1652 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1653 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1654 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1655 interconnect-names = "qup-core", 1656 "qup-config", 1657 "qup-memory"; 1658 1659 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1660 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1661 dma-names = "tx", 1662 "rx"; 1663 1664 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1665 pinctrl-names = "default"; 1666 1667 #address-cells = <1>; 1668 #size-cells = <0>; 1669 1670 status = "disabled"; 1671 }; 1672 1673 i2c12: i2c@a90000 { 1674 compatible = "qcom,geni-i2c"; 1675 reg = <0 0x00a90000 0 0x4000>; 1676 1677 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>; 1678 1679 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1680 clock-names = "se"; 1681 1682 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1683 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1684 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1685 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1686 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1687 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1688 interconnect-names = "qup-core", 1689 "qup-config", 1690 "qup-memory"; 1691 1692 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1693 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1694 dma-names = "tx", 1695 "rx"; 1696 1697 pinctrl-0 = <&qup_i2c12_data_clk>; 1698 pinctrl-names = "default"; 1699 1700 #address-cells = <1>; 1701 #size-cells = <0>; 1702 1703 status = "disabled"; 1704 }; 1705 1706 spi12: spi@a90000 { 1707 compatible = "qcom,geni-spi"; 1708 reg = <0 0x00a90000 0 0x4000>; 1709 1710 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>; 1711 1712 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1713 clock-names = "se"; 1714 1715 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1716 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1717 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1718 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1719 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1720 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1721 interconnect-names = "qup-core", 1722 "qup-config", 1723 "qup-memory"; 1724 1725 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1726 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1727 dma-names = "tx", 1728 "rx"; 1729 1730 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1731 pinctrl-names = "default"; 1732 1733 #address-cells = <1>; 1734 #size-cells = <0>; 1735 1736 status = "disabled"; 1737 }; 1738 1739 i2c13: i2c@a94000 { 1740 compatible = "qcom,geni-i2c"; 1741 reg = <0 0x00a94000 0 0x4000>; 1742 1743 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>; 1744 1745 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1746 clock-names = "se"; 1747 1748 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1749 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1750 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1751 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1752 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1753 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1754 interconnect-names = "qup-core", 1755 "qup-config", 1756 "qup-memory"; 1757 1758 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1759 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1760 dma-names = "tx", 1761 "rx"; 1762 1763 pinctrl-0 = <&qup_i2c13_data_clk>; 1764 pinctrl-names = "default"; 1765 1766 #address-cells = <1>; 1767 #size-cells = <0>; 1768 1769 status = "disabled"; 1770 }; 1771 1772 spi13: spi@a94000 { 1773 compatible = "qcom,geni-spi"; 1774 reg = <0 0x00a94000 0 0x4000>; 1775 1776 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>; 1777 1778 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1779 clock-names = "se"; 1780 1781 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1782 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1783 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1784 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1785 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1786 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1787 interconnect-names = "qup-core", 1788 "qup-config", 1789 "qup-memory"; 1790 1791 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1792 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1793 dma-names = "tx", 1794 "rx"; 1795 1796 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1797 pinctrl-names = "default"; 1798 1799 #address-cells = <1>; 1800 #size-cells = <0>; 1801 1802 status = "disabled"; 1803 }; 1804 1805 i2c14: i2c@a98000 { 1806 compatible = "qcom,geni-i2c"; 1807 reg = <0 0x00a98000 0 0x4000>; 1808 1809 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 1810 1811 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1812 clock-names = "se"; 1813 1814 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1815 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1816 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1817 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1818 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1819 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1820 interconnect-names = "qup-core", 1821 "qup-config", 1822 "qup-memory"; 1823 1824 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1825 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1826 dma-names = "tx", 1827 "rx"; 1828 1829 pinctrl-0 = <&qup_i2c14_data_clk>; 1830 pinctrl-names = "default"; 1831 1832 #address-cells = <1>; 1833 #size-cells = <0>; 1834 1835 status = "disabled"; 1836 }; 1837 1838 spi14: spi@a98000 { 1839 compatible = "qcom,geni-spi"; 1840 reg = <0 0x00a98000 0 0x4000>; 1841 1842 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 1843 1844 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1845 clock-names = "se"; 1846 1847 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1848 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1849 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1850 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1851 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1852 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1853 interconnect-names = "qup-core", 1854 "qup-config", 1855 "qup-memory"; 1856 1857 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1858 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1859 dma-names = "tx", 1860 "rx"; 1861 1862 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1863 pinctrl-names = "default"; 1864 1865 #address-cells = <1>; 1866 #size-cells = <0>; 1867 1868 status = "disabled"; 1869 }; 1870 1871 i2c15: i2c@a9c000 { 1872 compatible = "qcom,geni-i2c"; 1873 reg = <0 0x00a9c000 0 0x4000>; 1874 1875 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>; 1876 1877 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1878 clock-names = "se"; 1879 1880 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1881 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1882 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1883 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1884 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1885 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1886 interconnect-names = "qup-core", 1887 "qup-config", 1888 "qup-memory"; 1889 1890 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1891 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1892 dma-names = "tx", 1893 "rx"; 1894 1895 pinctrl-0 = <&qup_i2c15_data_clk>; 1896 pinctrl-names = "default"; 1897 1898 #address-cells = <1>; 1899 #size-cells = <0>; 1900 1901 status = "disabled"; 1902 }; 1903 1904 spi15: spi@a9c000 { 1905 compatible = "qcom,geni-spi"; 1906 reg = <0 0x00a9c000 0 0x4000>; 1907 1908 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>; 1909 1910 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1911 clock-names = "se"; 1912 1913 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1914 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1915 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1916 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1917 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1918 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1919 interconnect-names = "qup-core", 1920 "qup-config", 1921 "qup-memory"; 1922 1923 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1924 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1925 dma-names = "tx", 1926 "rx"; 1927 1928 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1929 pinctrl-names = "default"; 1930 1931 #address-cells = <1>; 1932 #size-cells = <0>; 1933 1934 status = "disabled"; 1935 }; 1936 }; 1937 1938 gpi_dma0: dma-controller@b00000 { 1939 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 1940 reg = <0 0x00b00000 0 0x60000>; 1941 1942 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1943 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1944 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1945 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1946 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1947 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1948 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1949 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1950 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1951 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1952 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 1953 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 1954 1955 dma-channels = <12>; 1956 dma-channel-mask = <0x3e>; 1957 #dma-cells = <3>; 1958 1959 iommus = <&apps_smmu 0x456 0x0>; 1960 1961 status = "disabled"; 1962 }; 1963 1964 qupv3_0: geniqup@bc0000 { 1965 compatible = "qcom,geni-se-qup"; 1966 reg = <0 0x00bc0000 0 0x2000>; 1967 1968 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1969 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1970 clock-names = "m-ahb", 1971 "s-ahb"; 1972 1973 iommus = <&apps_smmu 0x443 0x0>; 1974 #address-cells = <2>; 1975 #size-cells = <2>; 1976 ranges; 1977 1978 status = "disabled"; 1979 1980 i2c0: i2c@b80000 { 1981 compatible = "qcom,geni-i2c"; 1982 reg = <0 0xb80000 0 0x4000>; 1983 1984 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1985 1986 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1987 clock-names = "se"; 1988 1989 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1990 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1991 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1992 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1993 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1994 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1995 interconnect-names = "qup-core", 1996 "qup-config", 1997 "qup-memory"; 1998 1999 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 2000 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 2001 dma-names = "tx", 2002 "rx"; 2003 2004 pinctrl-0 = <&qup_i2c0_data_clk>; 2005 pinctrl-names = "default"; 2006 2007 #address-cells = <1>; 2008 #size-cells = <0>; 2009 2010 status = "disabled"; 2011 }; 2012 2013 spi0: spi@b80000 { 2014 compatible = "qcom,geni-spi"; 2015 reg = <0 0x00b80000 0 0x4000>; 2016 2017 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 2018 2019 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 2020 clock-names = "se"; 2021 2022 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2023 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2024 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2025 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2026 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2027 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2028 interconnect-names = "qup-core", 2029 "qup-config", 2030 "qup-memory"; 2031 2032 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 2033 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 2034 dma-names = "tx", 2035 "rx"; 2036 2037 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 2038 pinctrl-names = "default"; 2039 2040 #address-cells = <1>; 2041 #size-cells = <0>; 2042 2043 status = "disabled"; 2044 }; 2045 2046 i2c1: i2c@b84000 { 2047 compatible = "qcom,geni-i2c"; 2048 reg = <0 0x00b84000 0 0x4000>; 2049 2050 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2051 2052 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 2053 clock-names = "se"; 2054 2055 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2056 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2057 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2058 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2059 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2060 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2061 interconnect-names = "qup-core", 2062 "qup-config", 2063 "qup-memory"; 2064 2065 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 2066 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 2067 dma-names = "tx", 2068 "rx"; 2069 2070 pinctrl-0 = <&qup_i2c1_data_clk>; 2071 pinctrl-names = "default"; 2072 2073 #address-cells = <1>; 2074 #size-cells = <0>; 2075 2076 status = "disabled"; 2077 }; 2078 2079 spi1: spi@b84000 { 2080 compatible = "qcom,geni-spi"; 2081 reg = <0 0x00b84000 0 0x4000>; 2082 2083 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2084 2085 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 2086 clock-names = "se"; 2087 2088 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2089 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2090 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2091 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2092 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2093 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2094 interconnect-names = "qup-core", 2095 "qup-config", 2096 "qup-memory"; 2097 2098 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 2099 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 2100 dma-names = "tx", 2101 "rx"; 2102 2103 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 2104 pinctrl-names = "default"; 2105 2106 #address-cells = <1>; 2107 #size-cells = <0>; 2108 2109 status = "disabled"; 2110 }; 2111 2112 i2c2: i2c@b88000 { 2113 compatible = "qcom,geni-i2c"; 2114 reg = <0 0x00b88000 0 0x4000>; 2115 2116 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2117 2118 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2119 clock-names = "se"; 2120 2121 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2122 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2123 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2124 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2125 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2126 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2127 interconnect-names = "qup-core", 2128 "qup-config", 2129 "qup-memory"; 2130 2131 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 2132 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 2133 dma-names = "tx", 2134 "rx"; 2135 2136 pinctrl-0 = <&qup_i2c2_data_clk>; 2137 pinctrl-names = "default"; 2138 2139 #address-cells = <1>; 2140 #size-cells = <0>; 2141 2142 status = "disabled"; 2143 }; 2144 2145 spi2: spi@b88000 { 2146 compatible = "qcom,geni-spi"; 2147 reg = <0 0xb88000 0 0x4000>; 2148 2149 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2150 2151 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2152 clock-names = "se"; 2153 2154 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2155 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2156 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2157 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2158 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2159 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2160 interconnect-names = "qup-core", 2161 "qup-config", 2162 "qup-memory"; 2163 2164 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 2165 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 2166 dma-names = "tx", 2167 "rx"; 2168 2169 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 2170 pinctrl-names = "default"; 2171 2172 #address-cells = <1>; 2173 #size-cells = <0>; 2174 2175 status = "disabled"; 2176 }; 2177 2178 i2c3: i2c@b8c000 { 2179 compatible = "qcom,geni-i2c"; 2180 reg = <0 0x00b8c000 0 0x4000>; 2181 2182 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 2183 2184 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2185 clock-names = "se"; 2186 2187 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2188 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2189 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2190 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2191 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2192 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2193 interconnect-names = "qup-core", 2194 "qup-config", 2195 "qup-memory"; 2196 2197 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 2198 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 2199 dma-names = "tx", 2200 "rx"; 2201 2202 pinctrl-0 = <&qup_i2c3_data_clk>; 2203 pinctrl-names = "default"; 2204 2205 #address-cells = <1>; 2206 #size-cells = <0>; 2207 2208 status = "disabled"; 2209 }; 2210 2211 spi3: spi@b8c000 { 2212 compatible = "qcom,geni-spi"; 2213 reg = <0 0x00b8c000 0 0x4000>; 2214 2215 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 2216 2217 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2218 clock-names = "se"; 2219 2220 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2221 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2222 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2223 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2224 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2225 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2226 interconnect-names = "qup-core", 2227 "qup-config", 2228 "qup-memory"; 2229 2230 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 2231 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 2232 dma-names = "tx", 2233 "rx"; 2234 2235 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 2236 pinctrl-names = "default"; 2237 2238 #address-cells = <1>; 2239 #size-cells = <0>; 2240 2241 status = "disabled"; 2242 }; 2243 2244 i2c4: i2c@b90000 { 2245 compatible = "qcom,geni-i2c"; 2246 reg = <0 0xb90000 0 0x4000>; 2247 2248 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2249 2250 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2251 clock-names = "se"; 2252 2253 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2254 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2255 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2256 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2257 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2258 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2259 interconnect-names = "qup-core", 2260 "qup-config", 2261 "qup-memory"; 2262 2263 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 2264 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 2265 dma-names = "tx", 2266 "rx"; 2267 2268 pinctrl-0 = <&qup_i2c4_data_clk>; 2269 pinctrl-names = "default"; 2270 2271 #address-cells = <1>; 2272 #size-cells = <0>; 2273 2274 status = "disabled"; 2275 }; 2276 2277 spi4: spi@b90000 { 2278 compatible = "qcom,geni-spi"; 2279 reg = <0 0x00b90000 0 0x4000>; 2280 2281 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2282 2283 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2284 clock-names = "se"; 2285 2286 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2287 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2288 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2289 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2290 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2291 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2292 interconnect-names = "qup-core", 2293 "qup-config", 2294 "qup-memory"; 2295 2296 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 2297 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 2298 dma-names = "tx", 2299 "rx"; 2300 2301 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 2302 pinctrl-names = "default"; 2303 2304 #address-cells = <1>; 2305 #size-cells = <0>; 2306 2307 status = "disabled"; 2308 }; 2309 2310 i2c5: i2c@b94000 { 2311 compatible = "qcom,geni-i2c"; 2312 reg = <0 0x00b94000 0 0x4000>; 2313 2314 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 2315 2316 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2317 clock-names = "se"; 2318 2319 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2320 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2321 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2322 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2323 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2324 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2325 interconnect-names = "qup-core", 2326 "qup-config", 2327 "qup-memory"; 2328 2329 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 2330 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 2331 dma-names = "tx", 2332 "rx"; 2333 2334 pinctrl-0 = <&qup_i2c5_data_clk>; 2335 pinctrl-names = "default"; 2336 2337 #address-cells = <1>; 2338 #size-cells = <0>; 2339 2340 status = "disabled"; 2341 }; 2342 2343 spi5: spi@b94000 { 2344 compatible = "qcom,geni-spi"; 2345 reg = <0 0x00b94000 0 0x4000>; 2346 2347 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 2348 2349 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2350 clock-names = "se"; 2351 2352 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2353 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2354 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2355 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2356 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2357 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2358 interconnect-names = "qup-core", 2359 "qup-config", 2360 "qup-memory"; 2361 2362 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 2363 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 2364 dma-names = "tx", 2365 "rx"; 2366 2367 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 2368 pinctrl-names = "default"; 2369 2370 #address-cells = <1>; 2371 #size-cells = <0>; 2372 2373 status = "disabled"; 2374 }; 2375 2376 i2c6: i2c@b98000 { 2377 compatible = "qcom,geni-i2c"; 2378 reg = <0 0x00b98000 0 0x4000>; 2379 2380 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 2381 2382 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2383 clock-names = "se"; 2384 2385 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2386 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2387 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2388 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2389 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2390 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2391 interconnect-names = "qup-core", 2392 "qup-config", 2393 "qup-memory"; 2394 2395 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 2396 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 2397 dma-names = "tx", 2398 "rx"; 2399 2400 pinctrl-0 = <&qup_i2c6_data_clk>; 2401 pinctrl-names = "default"; 2402 2403 #address-cells = <1>; 2404 #size-cells = <0>; 2405 2406 status = "disabled"; 2407 }; 2408 2409 spi6: spi@b98000 { 2410 compatible = "qcom,geni-spi"; 2411 reg = <0 0x00b98000 0 0x4000>; 2412 2413 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 2414 2415 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2416 clock-names = "se"; 2417 2418 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2419 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2420 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2421 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2422 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2423 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2424 interconnect-names = "qup-core", 2425 "qup-config", 2426 "qup-memory"; 2427 2428 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 2429 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 2430 dma-names = "tx", 2431 "rx"; 2432 2433 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 2434 pinctrl-names = "default"; 2435 2436 #address-cells = <1>; 2437 #size-cells = <0>; 2438 2439 status = "disabled"; 2440 }; 2441 2442 i2c7: i2c@b9c000 { 2443 compatible = "qcom,geni-i2c"; 2444 reg = <0 0x00b9c000 0 0x4000>; 2445 2446 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 2447 2448 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2449 clock-names = "se"; 2450 2451 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2452 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2453 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2454 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2455 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2456 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2457 interconnect-names = "qup-core", 2458 "qup-config", 2459 "qup-memory"; 2460 2461 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 2462 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 2463 dma-names = "tx", 2464 "rx"; 2465 2466 pinctrl-0 = <&qup_i2c7_data_clk>; 2467 pinctrl-names = "default"; 2468 2469 #address-cells = <1>; 2470 #size-cells = <0>; 2471 2472 status = "disabled"; 2473 }; 2474 2475 spi7: spi@b9c000 { 2476 compatible = "qcom,geni-spi"; 2477 reg = <0 0x00b9c000 0 0x4000>; 2478 2479 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 2480 2481 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2482 clock-names = "se"; 2483 2484 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2485 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2486 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2487 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2488 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2489 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2490 interconnect-names = "qup-core", 2491 "qup-config", 2492 "qup-memory"; 2493 2494 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 2495 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 2496 dma-names = "tx", 2497 "rx"; 2498 2499 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 2500 pinctrl-names = "default"; 2501 2502 #address-cells = <1>; 2503 #size-cells = <0>; 2504 2505 status = "disabled"; 2506 }; 2507 }; 2508 2509 usb_1_ss0_hsphy: phy@fd3000 { 2510 compatible = "qcom,x1e80100-snps-eusb2-phy", 2511 "qcom,sm8550-snps-eusb2-phy"; 2512 reg = <0 0x00fd3000 0 0x154>; 2513 #phy-cells = <0>; 2514 2515 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2516 clock-names = "ref"; 2517 2518 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2519 2520 status = "disabled"; 2521 }; 2522 2523 usb_1_ss0_qmpphy: phy@fd5000 { 2524 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2525 reg = <0 0x00fd5000 0 0x4000>; 2526 2527 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2528 <&rpmhcc RPMH_CXO_CLK>, 2529 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2530 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2531 clock-names = "aux", 2532 "ref", 2533 "com_aux", 2534 "usb3_pipe"; 2535 2536 power-domains = <&gcc GCC_USB_0_PHY_GDSC>; 2537 2538 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2539 <&gcc GCC_USB4_0_DP0_PHY_PRIM_BCR>; 2540 reset-names = "phy", 2541 "common"; 2542 2543 #clock-cells = <1>; 2544 #phy-cells = <1>; 2545 2546 status = "disabled"; 2547 }; 2548 2549 usb_1_ss1_hsphy: phy@fd9000 { 2550 compatible = "qcom,x1e80100-snps-eusb2-phy", 2551 "qcom,sm8550-snps-eusb2-phy"; 2552 reg = <0 0x00fd9000 0 0x154>; 2553 #phy-cells = <0>; 2554 2555 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2556 clock-names = "ref"; 2557 2558 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2559 2560 status = "disabled"; 2561 }; 2562 2563 usb_1_ss1_qmpphy: phy@fda000 { 2564 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2565 reg = <0 0x00fda000 0 0x4000>; 2566 2567 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2568 <&rpmhcc RPMH_CXO_CLK>, 2569 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2570 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2571 clock-names = "aux", 2572 "ref", 2573 "com_aux", 2574 "usb3_pipe"; 2575 2576 power-domains = <&gcc GCC_USB_1_PHY_GDSC>; 2577 2578 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2579 <&gcc GCC_USB4_1_DP0_PHY_SEC_BCR>; 2580 reset-names = "phy", 2581 "common"; 2582 2583 #clock-cells = <1>; 2584 #phy-cells = <1>; 2585 2586 status = "disabled"; 2587 }; 2588 2589 usb_1_ss2_hsphy: phy@fde000 { 2590 compatible = "qcom,x1e80100-snps-eusb2-phy", 2591 "qcom,sm8550-snps-eusb2-phy"; 2592 reg = <0 0x00fde000 0 0x154>; 2593 #phy-cells = <0>; 2594 2595 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2596 clock-names = "ref"; 2597 2598 resets = <&gcc GCC_QUSB2PHY_TERT_BCR>; 2599 2600 status = "disabled"; 2601 }; 2602 2603 usb_1_ss2_qmpphy: phy@fdf000 { 2604 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2605 reg = <0 0x00fdf000 0 0x4000>; 2606 2607 clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, 2608 <&rpmhcc RPMH_CXO_CLK>, 2609 <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, 2610 <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>; 2611 clock-names = "aux", 2612 "ref", 2613 "com_aux", 2614 "usb3_pipe"; 2615 2616 power-domains = <&gcc GCC_USB_2_PHY_GDSC>; 2617 2618 resets = <&gcc GCC_USB3_PHY_TERT_BCR>, 2619 <&gcc GCC_USB4_2_DP0_PHY_TERT_BCR>; 2620 reset-names = "phy", 2621 "common"; 2622 2623 #clock-cells = <1>; 2624 #phy-cells = <1>; 2625 2626 status = "disabled"; 2627 }; 2628 2629 cnoc_main: interconnect@1500000 { 2630 compatible = "qcom,x1e80100-cnoc-main"; 2631 reg = <0 0x1500000 0 0x14400>; 2632 2633 qcom,bcm-voters = <&apps_bcm_voter>; 2634 2635 #interconnect-cells = <2>; 2636 }; 2637 2638 config_noc: interconnect@1600000 { 2639 compatible = "qcom,x1e80100-cnoc-cfg"; 2640 reg = <0 0x1600000 0 0x6600>; 2641 2642 qcom,bcm-voters = <&apps_bcm_voter>; 2643 2644 #interconnect-cells = <2>; 2645 }; 2646 2647 system_noc: interconnect@1680000 { 2648 compatible = "qcom,x1e80100-system-noc"; 2649 reg = <0 0x1680000 0 0x1c080>; 2650 2651 qcom,bcm-voters = <&apps_bcm_voter>; 2652 2653 #interconnect-cells = <2>; 2654 }; 2655 2656 pcie_south_anoc: interconnect@16c0000 { 2657 compatible = "qcom,x1e80100-pcie-south-anoc"; 2658 reg = <0 0x16c0000 0 0xd080>; 2659 2660 qcom,bcm-voters = <&apps_bcm_voter>; 2661 2662 #interconnect-cells = <2>; 2663 }; 2664 2665 pcie_center_anoc: interconnect@16d0000 { 2666 compatible = "qcom,x1e80100-pcie-center-anoc"; 2667 reg = <0 0x16d0000 0 0x7000>; 2668 2669 qcom,bcm-voters = <&apps_bcm_voter>; 2670 2671 #interconnect-cells = <2>; 2672 }; 2673 2674 aggre1_noc: interconnect@16e0000 { 2675 compatible = "qcom,x1e80100-aggre1-noc"; 2676 reg = <0 0x16E0000 0 0x14400>; 2677 2678 qcom,bcm-voters = <&apps_bcm_voter>; 2679 2680 #interconnect-cells = <2>; 2681 }; 2682 2683 aggre2_noc: interconnect@1700000 { 2684 compatible = "qcom,x1e80100-aggre2-noc"; 2685 reg = <0 0x1700000 0 0x1c400>; 2686 2687 qcom,bcm-voters = <&apps_bcm_voter>; 2688 2689 #interconnect-cells = <2>; 2690 }; 2691 2692 pcie_north_anoc: interconnect@1740000 { 2693 compatible = "qcom,x1e80100-pcie-north-anoc"; 2694 reg = <0 0x1740000 0 0x9080>; 2695 2696 qcom,bcm-voters = <&apps_bcm_voter>; 2697 2698 #interconnect-cells = <2>; 2699 }; 2700 2701 usb_center_anoc: interconnect@1750000 { 2702 compatible = "qcom,x1e80100-usb-center-anoc"; 2703 reg = <0 0x1750000 0 0x8800>; 2704 2705 qcom,bcm-voters = <&apps_bcm_voter>; 2706 2707 #interconnect-cells = <2>; 2708 }; 2709 2710 usb_north_anoc: interconnect@1760000 { 2711 compatible = "qcom,x1e80100-usb-north-anoc"; 2712 reg = <0 0x1760000 0 0x7080>; 2713 2714 qcom,bcm-voters = <&apps_bcm_voter>; 2715 2716 #interconnect-cells = <2>; 2717 }; 2718 2719 usb_south_anoc: interconnect@1770000 { 2720 compatible = "qcom,x1e80100-usb-south-anoc"; 2721 reg = <0 0x1770000 0 0xf080>; 2722 2723 qcom,bcm-voters = <&apps_bcm_voter>; 2724 2725 #interconnect-cells = <2>; 2726 }; 2727 2728 mmss_noc: interconnect@1780000 { 2729 compatible = "qcom,x1e80100-mmss-noc"; 2730 reg = <0 0x1780000 0 0x5B800>; 2731 2732 qcom,bcm-voters = <&apps_bcm_voter>; 2733 2734 #interconnect-cells = <2>; 2735 }; 2736 2737 pcie6a: pci@1bf8000 { 2738 device_type = "pci"; 2739 compatible = "qcom,pcie-x1e80100"; 2740 reg = <0 0x01bf8000 0 0x3000>, 2741 <0 0x70000000 0 0xf1d>, 2742 <0 0x70000f20 0 0xa8>, 2743 <0 0x70001000 0 0x1000>, 2744 <0 0x70100000 0 0x100000>; 2745 reg-names = "parf", 2746 "dbi", 2747 "elbi", 2748 "atu", 2749 "config"; 2750 #address-cells = <3>; 2751 #size-cells = <2>; 2752 ranges = <0x01000000 0 0x00000000 0 0x70200000 0 0x100000>, 2753 <0x02000000 0 0x70300000 0 0x70300000 0 0x3d00000>; 2754 bus-range = <0 0xff>; 2755 2756 dma-coherent; 2757 2758 linux,pci-domain = <7>; 2759 num-lanes = <2>; 2760 2761 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 2762 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 2763 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 2764 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 2765 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 2766 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 2767 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 2768 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>; 2769 interrupt-names = "msi0", 2770 "msi1", 2771 "msi2", 2772 "msi3", 2773 "msi4", 2774 "msi5", 2775 "msi6", 2776 "msi7"; 2777 2778 #interrupt-cells = <1>; 2779 interrupt-map-mask = <0 0 0 0x7>; 2780 interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>, 2781 <0 0 0 2 &intc 0 0 0 844 IRQ_TYPE_LEVEL_HIGH>, 2782 <0 0 0 3 &intc 0 0 0 845 IRQ_TYPE_LEVEL_HIGH>, 2783 <0 0 0 4 &intc 0 0 0 772 IRQ_TYPE_LEVEL_HIGH>; 2784 2785 clocks = <&gcc GCC_PCIE_6A_AUX_CLK>, 2786 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, 2787 <&gcc GCC_PCIE_6A_MSTR_AXI_CLK>, 2788 <&gcc GCC_PCIE_6A_SLV_AXI_CLK>, 2789 <&gcc GCC_PCIE_6A_SLV_Q2A_AXI_CLK>, 2790 <&gcc GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK>, 2791 <&gcc GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK>; 2792 clock-names = "aux", 2793 "cfg", 2794 "bus_master", 2795 "bus_slave", 2796 "slave_q2a", 2797 "noc_aggr", 2798 "cnoc_sf_axi"; 2799 2800 assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>; 2801 assigned-clock-rates = <19200000>; 2802 2803 interconnects = <&pcie_south_anoc MASTER_PCIE_6A QCOM_ICC_TAG_ALWAYS 2804 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2805 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2806 &cnoc_main SLAVE_PCIE_6A QCOM_ICC_TAG_ALWAYS>; 2807 interconnect-names = "pcie-mem", 2808 "cpu-pcie"; 2809 2810 resets = <&gcc GCC_PCIE_6A_BCR>, 2811 <&gcc GCC_PCIE_6A_LINK_DOWN_BCR>; 2812 reset-names = "pci", 2813 "link_down"; 2814 2815 power-domains = <&gcc GCC_PCIE_6A_GDSC>; 2816 2817 phys = <&pcie6a_phy>; 2818 phy-names = "pciephy"; 2819 2820 status = "disabled"; 2821 }; 2822 2823 pcie6a_phy: phy@1bfc000 { 2824 compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy"; 2825 reg = <0 0x01bfc000 0 0x2000>; 2826 2827 clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>, 2828 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, 2829 <&rpmhcc RPMH_CXO_CLK>, 2830 <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>, 2831 <&gcc GCC_PCIE_6A_PIPE_CLK>; 2832 clock-names = "aux", 2833 "cfg_ahb", 2834 "ref", 2835 "rchng", 2836 "pipe"; 2837 2838 resets = <&gcc GCC_PCIE_6A_PHY_BCR>, 2839 <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>; 2840 reset-names = "phy", 2841 "phy_nocsr"; 2842 2843 assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>; 2844 assigned-clock-rates = <100000000>; 2845 2846 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>; 2847 2848 #clock-cells = <0>; 2849 clock-output-names = "pcie6a_pipe_clk"; 2850 2851 #phy-cells = <0>; 2852 2853 status = "disabled"; 2854 }; 2855 2856 pcie4: pci@1c08000 { 2857 device_type = "pci"; 2858 compatible = "qcom,pcie-x1e80100"; 2859 reg = <0 0x01c08000 0 0x3000>, 2860 <0 0x7c000000 0 0xf1d>, 2861 <0 0x7c000f40 0 0xa8>, 2862 <0 0x7c001000 0 0x1000>, 2863 <0 0x7c100000 0 0x100000>, 2864 <0 0x01c0b000 0 0x1000>; 2865 reg-names = "parf", 2866 "dbi", 2867 "elbi", 2868 "atu", 2869 "config", 2870 "mhi"; 2871 #address-cells = <3>; 2872 #size-cells = <2>; 2873 ranges = <0x01000000 0 0x00000000 0 0x7c200000 0 0x100000>, 2874 <0x02000000 0 0x7c300000 0 0x7c300000 0 0x3d00000>; 2875 bus-range = <0x00 0xff>; 2876 2877 dma-coherent; 2878 2879 linux,pci-domain = <5>; 2880 num-lanes = <2>; 2881 2882 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2883 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2884 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2885 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2886 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2887 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2888 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2889 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2890 interrupt-names = "msi0", 2891 "msi1", 2892 "msi2", 2893 "msi3", 2894 "msi4", 2895 "msi5", 2896 "msi6", 2897 "msi7"; 2898 2899 #interrupt-cells = <1>; 2900 interrupt-map-mask = <0 0 0 0x7>; 2901 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, 2902 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, 2903 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, 2904 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; 2905 2906 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 2907 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 2908 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 2909 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 2910 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 2911 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 2912 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 2913 clock-names = "aux", 2914 "cfg", 2915 "bus_master", 2916 "bus_slave", 2917 "slave_q2a", 2918 "noc_aggr", 2919 "cnoc_sf_axi"; 2920 2921 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 2922 assigned-clock-rates = <19200000>; 2923 2924 interconnects = <&pcie_south_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS 2925 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2926 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2927 &cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>; 2928 interconnect-names = "pcie-mem", 2929 "cpu-pcie"; 2930 2931 resets = <&gcc GCC_PCIE_4_BCR>, 2932 <&gcc GCC_PCIE_4_LINK_DOWN_BCR>; 2933 reset-names = "pci", 2934 "link_down"; 2935 2936 power-domains = <&gcc GCC_PCIE_4_GDSC>; 2937 2938 phys = <&pcie4_phy>; 2939 phy-names = "pciephy"; 2940 2941 status = "disabled"; 2942 }; 2943 2944 pcie4_phy: phy@1c0e000 { 2945 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy"; 2946 reg = <0 0x01c0e000 0 0x2000>; 2947 2948 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 2949 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 2950 <&rpmhcc RPMH_CXO_CLK>, 2951 <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, 2952 <&gcc GCC_PCIE_4_PIPE_CLK>; 2953 clock-names = "aux", 2954 "cfg_ahb", 2955 "ref", 2956 "rchng", 2957 "pipe"; 2958 2959 resets = <&gcc GCC_PCIE_4_PHY_BCR>; 2960 reset-names = "phy"; 2961 2962 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; 2963 assigned-clock-rates = <100000000>; 2964 2965 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>; 2966 2967 #clock-cells = <0>; 2968 clock-output-names = "pcie4_pipe_clk"; 2969 2970 #phy-cells = <0>; 2971 2972 status = "disabled"; 2973 }; 2974 2975 tcsr_mutex: hwlock@1f40000 { 2976 compatible = "qcom,tcsr-mutex"; 2977 reg = <0 0x01f40000 0 0x20000>; 2978 #hwlock-cells = <1>; 2979 }; 2980 2981 tcsr: clock-controller@1fc0000 { 2982 compatible = "qcom,x1e80100-tcsr", "syscon"; 2983 reg = <0 0x01fc0000 0 0x30000>; 2984 clocks = <&rpmhcc RPMH_CXO_CLK>; 2985 #clock-cells = <1>; 2986 #reset-cells = <1>; 2987 }; 2988 2989 gpu: gpu@3d00000 { 2990 compatible = "qcom,adreno-43050c01", "qcom,adreno"; 2991 reg = <0x0 0x03d00000 0x0 0x40000>, 2992 <0x0 0x03d61000 0x0 0x800>, 2993 <0x0 0x03d9e000 0x0 0x1000>; 2994 2995 reg-names = "kgsl_3d0_reg_memory", 2996 "cx_dbgc", 2997 "cx_mem"; 2998 2999 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 3000 3001 iommus = <&adreno_smmu 0 0x0>, 3002 <&adreno_smmu 1 0x0>; 3003 3004 operating-points-v2 = <&gpu_opp_table>; 3005 3006 qcom,gmu = <&gmu>; 3007 #cooling-cells = <2>; 3008 3009 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 3010 interconnect-names = "gfx-mem"; 3011 3012 zap-shader { 3013 memory-region = <&gpu_microcode_mem>; 3014 firmware-name = "qcom/gen70500_zap.mbn"; 3015 }; 3016 3017 gpu_opp_table: opp-table { 3018 compatible = "operating-points-v2"; 3019 3020 opp-1100000000 { 3021 opp-hz = /bits/ 64 <1100000000>; 3022 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3023 opp-peak-kBps = <16500000>; 3024 }; 3025 3026 opp-1000000000 { 3027 opp-hz = /bits/ 64 <1000000000>; 3028 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3029 opp-peak-kBps = <14398438>; 3030 }; 3031 3032 opp-925000000 { 3033 opp-hz = /bits/ 64 <925000000>; 3034 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3035 opp-peak-kBps = <14398438>; 3036 }; 3037 3038 opp-800000000 { 3039 opp-hz = /bits/ 64 <800000000>; 3040 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3041 opp-peak-kBps = <12449219>; 3042 }; 3043 3044 opp-744000000 { 3045 opp-hz = /bits/ 64 <744000000>; 3046 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3047 opp-peak-kBps = <10687500>; 3048 }; 3049 3050 opp-687000000 { 3051 opp-hz = /bits/ 64 <687000000>; 3052 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3053 opp-peak-kBps = <8171875>; 3054 }; 3055 3056 opp-550000000 { 3057 opp-hz = /bits/ 64 <550000000>; 3058 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3059 opp-peak-kBps = <6074219>; 3060 }; 3061 3062 opp-390000000 { 3063 opp-hz = /bits/ 64 <390000000>; 3064 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3065 opp-peak-kBps = <3000000>; 3066 }; 3067 3068 opp-300000000 { 3069 opp-hz = /bits/ 64 <300000000>; 3070 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 3071 opp-peak-kBps = <2136719>; 3072 }; 3073 }; 3074 }; 3075 > 3076 gmu: gmu@3d6a000 {
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 5f90a0b3c016..3e887286bab4 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,x1e80100-dispcc.h> #include <dt-bindings/clock/qcom,x1e80100-gcc.h> +#include <dt-bindings/clock/qcom,x1e80100-gpucc.h> #include <dt-bindings/clock/qcom,x1e80100-tcsr.h> #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/interconnect/qcom,icc.h> @@ -2985,6 +2986,200 @@ tcsr: clock-controller@1fc0000 { #reset-cells = <1>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-43050c01", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d61000 0x0 0x800>, + <0x0 0x03d9e000 0x0 0x1000>; + + reg-names = "kgsl_3d0_reg_memory", + "cx_dbgc", + "cx_mem"; + + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; + + iommus = <&adreno_smmu 0 0x0>, + <&adreno_smmu 1 0x0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + #cooling-cells = <2>; + + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "gfx-mem"; + + zap-shader { + memory-region = <&gpu_microcode_mem>; + firmware-name = "qcom/gen70500_zap.mbn"; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + opp-peak-kBps = <16500000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + opp-peak-kBps = <14398438>; + }; + + opp-925000000 { + opp-hz = /bits/ 64 <925000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + opp-peak-kBps = <14398438>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + opp-peak-kBps = <12449219>; + }; + + opp-744000000 { + opp-hz = /bits/ 64 <744000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; + opp-peak-kBps = <10687500>; + }; + + opp-687000000 { + opp-hz = /bits/ 64 <687000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + opp-peak-kBps = <8171875>; + }; + + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + opp-peak-kBps = <6074219>; + }; + + opp-390000000 { + opp-hz = /bits/ 64 <390000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + opp-peak-kBps = <3000000>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; + opp-peak-kBps = <2136719>; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu"; + reg = <0x0 0x03d50000 0x0 0x10000>, + <0x0 0x03d6a000 0x0 0x35000>, + <0x0 0x0b280000 0x0 0x10000>; + reg-names = "rscc", "gmu", "gmu_pdc"; + + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_DEMET_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "axi", + "memnoc", + "hub", + "demet"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x0>; + + qcom,qmp = <&aoss_qmp>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + opp-220000000 { + opp-hz = /bits/ 64 <220000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + }; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,x1e80100-gpucc"; + reg = <0 0x03d90000 0 0xa000>; + clocks = <&bi_tcxo_div2>, + <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + adreno_smmu: iommu@3da0000 { + compatible = "qcom,x1e80100-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = "hlos", + "bus", + "iface", + "ahb"; + power-domains = <&gpucc GPU_CX_GDSC>; + dma-coherent; + }; + gem_noc: interconnect@26400000 { compatible = "qcom,x1e80100-gem-noc"; reg = <0 0x26400000 0 0x311200>;
Add the necessary dt nodes for gpu support in X1E80100. Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 195 +++++++++++++++++++++++++ 1 file changed, 195 insertions(+)