| Message ID | 20240628142347.1283015-6-peter.maydell@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/arm: Refactor FPCR/FPSR handling to prepare for FEAT_AFP | expand |
On 6/28/24 07:23, Peter Maydell wrote: > We already have a load_cpu_field_low32() to load the low half of a > 64-bit CPU struct field to a TCGv_i32; however we haven't yet needed > the store equivalent. We'll want that in the next patch, so > implement it. > > Signed-off-by: Peter Maydell<peter.maydell@linaro.org> > --- > target/arm/tcg/translate-a32.h | 7 +++++++ > 1 file changed, 7 insertions(+) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/arm/tcg/translate-a32.h b/target/arm/tcg/translate-a32.h index 19de6e0a1a9..0b1fa57965c 100644 --- a/target/arm/tcg/translate-a32.h +++ b/target/arm/tcg/translate-a32.h @@ -83,6 +83,13 @@ void store_cpu_offset(TCGv_i32 var, int offset, int size); sizeof_field(CPUARMState, name)); \ }) +/* Store to the low half of a 64-bit field from a TCGv_i32 */ +#define store_cpu_field_low32(val, name) \ + ({ \ + QEMU_BUILD_BUG_ON(sizeof_field(CPUARMState, name) != 8); \ + store_cpu_offset(val, offsetoflow32(CPUARMState, name), 4); \ + }) + #define store_cpu_field_constant(val, name) \ store_cpu_field(tcg_constant_i32(val), name)
We already have a load_cpu_field_low32() to load the low half of a 64-bit CPU struct field to a TCGv_i32; however we haven't yet needed the store equivalent. We'll want that in the next patch, so implement it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/tcg/translate-a32.h | 7 +++++++ 1 file changed, 7 insertions(+)