| Message ID | 20240629-camss_first_post_linux_next-v1-1-bc798edabc3a@quicinc.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | media: qcom: camss: Add sc7280 support | expand |
On 28/06/2024 19:32, Vikram Sharma wrote: > Add bindings for qcom,sc7280-camss in order to support the camera > subsystem for sc7280. > > Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com> > Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com> > Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> > --- > .../bindings/media/qcom,sc7280-camss.yaml | 477 +++++++++++++++++++++ > 1 file changed, 477 insertions(+) > > diff --git a/Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml > new file mode 100644 > index 000000000000..588c6fb50e2f > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml > @@ -0,0 +1,477 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > + > +--- > +$id: http://devicetree.org/schemas/media/qcom,sc7280-camss.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Technologies, Inc. SC7280 CAMSS ISP > + > +maintainers: > + - Azam Sadiq Pasha Kapatrala Syed <akapatra@quicinc.com> > + - Hariram Purushothaman <hariramp@quicinc.com> > + > +description: | > + The CAMSS IP is a CSI decoder and ISP present on > + Qualcomm Technologies, Inc. platforms. > + > +properties: > + compatible: > + const: qcom,sc7280-camss > + > + clocks: > + minItems: 41 > + maxItems: 41 > + > + clock-names: > + items: > + > + - const: cam_hf_axi > + - const: slow_ahb_src > + - const: cpas_ahb > + - const: camnoc_axi_src You almost certainly don't need to include the "_src" clocks in the list of clocks since the CAMCC driver lists "someclock" as having parent "someclock_src" > + - const: camnoc_axi > + - const: csiphy0 > + - const: csiphy0_timer > + - const: csiphy0_timer_src > + - const: csiphy1 > + - const: csiphy1_timer > + - const: csiphy1_timer_src > + - const: csiphy2 > + - const: csiphy2_timer > + - const: csiphy2_timer_src > + - const: csiphy3 > + - const: csiphy3_timer > + - const: csiphy3_timer_src > + - const: csiphy4 > + - const: csiphy4_timer > + - const: csiphy4_timer_src > + - const: vfe0_csid > + - const: vfe0_cphy_rx > + - const: vfe0 > + - const: vfe0_axi > + - const: csiphy_rx_src > + - const: vfe1_csid > + - const: vfe1_cphy_rx > + - const: vfe1 > + - const: vfe1_axi > + - const: vfe2_csid > + - const: vfe2_cphy_rx > + - const: vfe2 > + - const: vfe2_axi > + - const: vfe0_lite_csid > + - const: vfe0_lite_cphy_rx > + - const: vfe0_lite > + - const: vfe1_lite_csid > + - const: vfe1_lite_cphy_rx > + - const: vfe1_lite > + - const: vfe_lite0 > + - const: vfe_lite1 > + > + interrupts: > + minItems: 15 > + maxItems: 15 > + > + interrupt-names: > + items: > + - const: csiphy0 > + - const: csiphy1 > + - const: csiphy2 > + - const: csiphy3 > + - const: csiphy4 > + - const: csid0 > + - const: csid1 > + - const: csid2 > + - const: csid_lite0 > + - const: csid_lite1 > + - const: vfe0 > + - const: vfe1 > + - const: vfe2 > + - const: vfe_lite0 > + - const: vfe_lite1 > + > + iommus: > + maxItems: 1 > + > + interconnects: > + minItems: 2 > + maxItems: 2 > + > + interconnect-names: > + items: > + - const: cam_ahb > + - const: cam_hf_0 > + > + power-domains: > + items: > + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. Please name these power domains. https://lore.kernel.org/linux-arm-msm/fcdb072d-6099-4423-b4b5-21e9052b82cc@linaro.org/ --- bod
On 28/06/2024 20:32, Vikram Sharma wrote: > Add bindings for qcom,sc7280-camss in order to support the camera > subsystem for sc7280. > > Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com> > Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com> > Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> > --- > .../bindings/media/qcom,sc7280-camss.yaml | 477 +++++++++++++++++++++ > 1 file changed, 477 insertions(+) > > diff --git a/Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml > new file mode 100644 > index 000000000000..588c6fb50e2f > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml > @@ -0,0 +1,477 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > + > +--- > +$id: http://devicetree.org/schemas/media/qcom,sc7280-camss.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Technologies, Inc. SC7280 CAMSS ISP We write only "Qualcomm", drop "Technologies, Inc.". > + > +maintainers: > + - Azam Sadiq Pasha Kapatrala Syed <akapatra@quicinc.com> > + - Hariram Purushothaman <hariramp@quicinc.com> > + > +description: | Do not need '|' unless you need to preserve formatting. > + The CAMSS IP is a CSI decoder and ISP present on > + Qualcomm Technologies, Inc. platforms. > + > +properties: > + compatible: > + const: qcom,sc7280-camss > + > + clocks: > + minItems: 41 Drop > + maxItems: 41 > + > + clock-names: > + items: > + Drop blank line > + - const: cam_hf_axi > + - const: slow_ahb_src > + - const: cpas_ahb > + - const: camnoc_axi_src > + - const: camnoc_axi Which file did you use as template? Isn't this supposed to be reversed? BTW, you *must* work on latest tree. Do not take some ancient code and use as template. It's really waste of time to point the same issues over and over again. > + - const: csiphy0 > + - const: csiphy0_timer > + - const: csiphy0_timer_src > + - const: csiphy1 > + - const: csiphy1_timer > + - const: csiphy1_timer_src > + - const: csiphy2 > + - const: csiphy2_timer > + - const: csiphy2_timer_src > + - const: csiphy3 > + - const: csiphy3_timer > + - const: csiphy3_timer_src > + - const: csiphy4 > + - const: csiphy4_timer > + - const: csiphy4_timer_src > + - const: vfe0_csid > + - const: vfe0_cphy_rx > + - const: vfe0 > + - const: vfe0_axi > + - const: csiphy_rx_src > + - const: vfe1_csid > + - const: vfe1_cphy_rx > + - const: vfe1 > + - const: vfe1_axi > + - const: vfe2_csid > + - const: vfe2_cphy_rx > + - const: vfe2 > + - const: vfe2_axi > + - const: vfe0_lite_csid > + - const: vfe0_lite_cphy_rx Why these are reversed comparing to other bindings? Srsly, from which file did you take it? > + - const: vfe0_lite > + - const: vfe1_lite_csid > + - const: vfe1_lite_cphy_rx > + - const: vfe1_lite > + - const: vfe_lite0 > + - const: vfe_lite1 > + > + interrupts: > + minItems: 15 Drop > + maxItems: 15 > + > + interrupt-names: > + items: > + - const: csiphy0 > + - const: csiphy1 > + - const: csiphy2 > + - const: csiphy3 > + - const: csiphy4 > + - const: csid0 > + - const: csid1 > + - const: csid2 > + - const: csid_lite0 > + - const: csid_lite1 > + - const: vfe0 > + - const: vfe1 > + - const: vfe2 > + - const: vfe_lite0 > + - const: vfe_lite1 > + > + iommus: > + maxItems: 1 > + > + interconnects: > + minItems: 2 Drop > + maxItems: 2 > + > + interconnect-names: > + items: > + - const: cam_ahb > + - const: cam_hf_0 Drop "cam_" prefix in both. Actually everywhere... > + > + power-domains: > + items: > + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + description: > + CSI input ports. > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: > + Input port for receiving CSI data. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + clock-lanes: > + maxItems: 1 > + > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + required: > + - clock-lanes > + - data-lanes > + > + port@1: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: > + Input port for receiving CSI data. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + clock-lanes: > + maxItems: 1 > + > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + required: > + - clock-lanes > + - data-lanes > + > + port@2: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: > + Input port for receiving CSI data. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + clock-lanes: > + maxItems: 1 > + > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + required: > + - clock-lanes > + - data-lanes > + > + port@3: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: > + Input port for receiving CSI data. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + clock-lanes: > + maxItems: 1 > + > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + required: > + - clock-lanes > + - data-lanes > + > + port@4: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: > + Input port for receiving CSI data. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + clock-lanes: > + maxItems: 1 > + > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + required: > + - clock-lanes > + - data-lanes > + > + port@5: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: > + Input port for receiving CSI data. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + clock-lanes: > + maxItems: 1 > + > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + required: > + - clock-lanes > + - data-lanes > + > + reg: > + minItems: 10 Drop > + maxItems: 10 > + > + reg-names: > + items: > + - const: vfe0 > + - const: vfe1 > + - const: vfe2 > + - const: vfe_lite0 > + - const: vfe_lite1 > + - const: csiphy0 > + - const: csiphy1 > + - const: csiphy2 > + - const: csiphy3 > + - const: csiphy4 Which file did you use as template for these? > + > +required: > + - clock-names > + - clocks > + - compatible > + - interconnects > + - interconnect-names > + - interrupts > + - interrupt-names > + - iommus > + - power-domains > + - reg > + - reg-names > + > +additionalProperties: false Missing blank line > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/clock/qcom,camcc-sc7280.h> > + #include <dt-bindings/interconnect/qcom,sc7280.h> > + #include <dt-bindings/clock/qcom,gcc-sc7280.h> > + #include <dt-bindings/power/qcom-rpmpd.h> These should be in alphabetical order, not random. > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + camss: camss@acaf000 { > + compatible = "qcom,sc7280-camss"; > + reg = <0x0 0x0acaf000 0x0 0x5200>, > + <0x0 0x0acb6000 0x0 0x5200>, > + <0x0 0x0acbd000 0x0 0x5200>, > + <0x0 0x0acc4000 0x0 0x5000>, > + <0x0 0x0accb000 0x0 0x5000>, > + <0x0 0x0ace0000 0x0 0x2000>, > + <0x0 0x0ace2000 0x0 0x2000>, > + <0x0 0x0ace4000 0x0 0x2000>, > + <0x0 0x0ace6000 0x0 0x2000>, > + <0x0 0x0ace8000 0x0 0x2000>; > + > + reg-names = "vfe0", > + "vfe1", > + "vfe2", Misaligned. > + "vfe_lite0", > + "vfe_lite1", > + "csiphy0", > + "csiphy1", > + "csiphy2", > + "csiphy3", > + "csiphy4"; > + > + interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, Misaligned. > + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>; > + > + interrupt-names = "csiphy0", > + "csiphy1", > + "csiphy2", Misaligned. > + "csiphy3", > + "csiphy4", > + "csid0", > + "csid1", > + "csid2", > + "csid_lite0", > + "csid_lite1", > + "vfe0", > + "vfe1", > + "vfe2", > + "vfe_lite0", > + "vfe_lite1"; Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml new file mode 100644 index 000000000000..588c6fb50e2f --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml @@ -0,0 +1,477 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 + +--- +$id: http://devicetree.org/schemas/media/qcom,sc7280-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SC7280 CAMSS ISP + +maintainers: + - Azam Sadiq Pasha Kapatrala Syed <akapatra@quicinc.com> + - Hariram Purushothaman <hariramp@quicinc.com> + +description: | + The CAMSS IP is a CSI decoder and ISP present on + Qualcomm Technologies, Inc. platforms. + +properties: + compatible: + const: qcom,sc7280-camss + + clocks: + minItems: 41 + maxItems: 41 + + clock-names: + items: + + - const: cam_hf_axi + - const: slow_ahb_src + - const: cpas_ahb + - const: camnoc_axi_src + - const: camnoc_axi + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy0_timer_src + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy1_timer_src + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy2_timer_src + - const: csiphy3 + - const: csiphy3_timer + - const: csiphy3_timer_src + - const: csiphy4 + - const: csiphy4_timer + - const: csiphy4_timer_src + - const: vfe0_csid + - const: vfe0_cphy_rx + - const: vfe0 + - const: vfe0_axi + - const: csiphy_rx_src + - const: vfe1_csid + - const: vfe1_cphy_rx + - const: vfe1 + - const: vfe1_axi + - const: vfe2_csid + - const: vfe2_cphy_rx + - const: vfe2 + - const: vfe2_axi + - const: vfe0_lite_csid + - const: vfe0_lite_cphy_rx + - const: vfe0_lite + - const: vfe1_lite_csid + - const: vfe1_lite_cphy_rx + - const: vfe1_lite + - const: vfe_lite0 + - const: vfe_lite1 + + interrupts: + minItems: 15 + maxItems: 15 + + interrupt-names: + items: + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + + iommus: + maxItems: 1 + + interconnects: + minItems: 2 + maxItems: 2 + + interconnect-names: + items: + - const: cam_ahb + - const: cam_hf_0 + + power-domains: + items: + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller. + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@2: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@3: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@4: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@5: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + reg: + minItems: 10 + maxItems: 10 + + reg-names: + items: + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + +required: + - clock-names + - clocks + - compatible + - interconnects + - interconnect-names + - interrupts + - interrupt-names + - iommus + - power-domains + - reg + - reg-names + +additionalProperties: false +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/qcom,camcc-sc7280.h> + #include <dt-bindings/interconnect/qcom,sc7280.h> + #include <dt-bindings/clock/qcom,gcc-sc7280.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + camss: camss@acaf000 { + compatible = "qcom,sc7280-camss"; + reg = <0x0 0x0acaf000 0x0 0x5200>, + <0x0 0x0acb6000 0x0 0x5200>, + <0x0 0x0acbd000 0x0 0x5200>, + <0x0 0x0acc4000 0x0 0x5000>, + <0x0 0x0accb000 0x0 0x5000>, + <0x0 0x0ace0000 0x0 0x2000>, + <0x0 0x0ace2000 0x0 0x2000>, + <0x0 0x0ace4000 0x0 0x2000>, + <0x0 0x0ace6000 0x0 0x2000>, + <0x0 0x0ace8000 0x0 0x2000>; + + reg-names = "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4"; + + interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, + <&camcc CAM_CC_IFE_1_GDSC>, + <&camcc CAM_CC_IFE_2_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + + clocks = <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CSID_CLK>, + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CSID_CLK>, + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>, + <&camcc CAM_CC_IFE_2_CSID_CLK>, + <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_2_CLK>, + <&camcc CAM_CC_IFE_2_AXI_CLK>, + <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_0_CLK>, + <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_1_CLK>, + <&camcc CAM_CC_IFE_LITE_0_CLK>, + <&camcc CAM_CC_IFE_LITE_1_CLK>; + + clock-names = "cam_hf_axi", + "slow_ahb_src", + "cpas_ahb", + "camnoc_axi_src", + "camnoc_axi", + "csiphy0", + "csiphy0_timer", + "csiphy0_timer_src", + "csiphy1", + "csiphy1_timer", + "csiphy1_timer_src", + "csiphy2", + "csiphy2_timer", + "csiphy2_timer_src", + "csiphy3", + "csiphy3_timer", + "csiphy3_timer_src", + "csiphy4", + "csiphy4_timer", + "csiphy4_timer_src", + "vfe0_csid", + "vfe0_cphy_rx", + "vfe0", + "vfe0_axi", + "csiphy_rx_src", + "vfe1_csid", + "vfe1_cphy_rx", + "vfe1", + "vfe1_axi", + "vfe2_csid", + "vfe2_cphy_rx", + "vfe2", + "vfe2_axi", + "vfe0_lite_csid", + "vfe0_lite_cphy_rx", + "vfe0_lite", + "vfe1_lite_csid", + "vfe1_lite_cphy_rx", + "vfe1_lite", + "vfe_lite0", + "vfe_lite1"; + + iommus = <&apps_smmu 0x800 0x4e0>; + + interconnect-names = "cam_ahb", "cam_hf_0"; + + interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_CAMERA_CFG 0>, + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + + port@4 { + reg = <4>; + }; + }; + }; + };