Message ID | 20240628223506.1237523-4-peter.griffin@linaro.org (mailing list archive) |
---|---|
State | Accepted |
Commit | 85863cee8ce0c3f4d0010e78feb664fb26c35e95 |
Headers | show |
Series | Add syscon-reboot and syscon-poweroff support for gs101/Pixel 6 | expand |
On Fri, 28 Jun 2024 23:35:05 +0100, Peter Griffin wrote: > Not all registers in PMU_ALIVE block support atomic set/clear operations. > GS101_SYSIP_DAT0 and GS101_SYSTEM_CONFIGURATION registers are two regs > where attempting atomic access fails. > > As documentation on exactly which registers support atomic operations is > not forthcoming. We default to atomic access, unless the register is > explicitly added to the tensor_is_atomic() function. Update the comment > to reflect this as well. > > [...] Applied, thanks! [2/3] soc: samsung: exynos-pmu: add support for PMU_ALIVE non atomic registers https://git.kernel.org/krzk/linux/c/85863cee8ce0c3f4d0010e78feb664fb26c35e95 Best regards,
diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c index 624324f4001c..d8c53cec7f37 100644 --- a/drivers/soc/samsung/exynos-pmu.c +++ b/drivers/soc/samsung/exynos-pmu.c @@ -129,14 +129,30 @@ static int tensor_set_bits_atomic(void *ctx, unsigned int offset, u32 val, return ret; } -static int tensor_sec_update_bits(void *ctx, unsigned int reg, - unsigned int mask, unsigned int val) +static bool tensor_is_atomic(unsigned int reg) { /* * Use atomic operations for PMU_ALIVE registers (offset 0~0x3FFF) - * as the target registers can be accessed by multiple masters. + * as the target registers can be accessed by multiple masters. SFRs + * that don't support atomic are added to the switch statement below. */ if (reg > PMUALIVE_MASK) + return false; + + switch (reg) { + case GS101_SYSIP_DAT0: + case GS101_SYSTEM_CONFIGURATION: + return false; + default: + return true; + } +} + +static int tensor_sec_update_bits(void *ctx, unsigned int reg, + unsigned int mask, unsigned int val) +{ + + if (!tensor_is_atomic(reg)) return tensor_sec_reg_rmw(ctx, reg, mask, val); return tensor_set_bits_atomic(ctx, reg, val, mask); diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/soc/samsung/exynos-regs-pmu.h index aa840ed043e1..f411c176536d 100644 --- a/include/linux/soc/samsung/exynos-regs-pmu.h +++ b/include/linux/soc/samsung/exynos-regs-pmu.h @@ -657,4 +657,8 @@ #define EXYNOS5433_PAD_RETENTION_UFS_OPTION (0x3268) #define EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION (0x32A8) +/* For Tensor GS101 */ +#define GS101_SYSIP_DAT0 (0x810) +#define GS101_SYSTEM_CONFIGURATION (0x3A00) + #endif /* __LINUX_SOC_EXYNOS_REGS_PMU_H */