[v3,0/6] USB31DRD phy support for Google Tensor gs101 (HS & SS)

Message

André Draszik June 17, 2024, 4:44 p.m. UTC

This patch series adds support for the Exynos USB 3.1 DRD combo phy, as
found in Exynos 9 SoCs like Google GS101. It supports USB SS, HS and
DisplayPort, but DisplayPort is out of scope for this series.

In terms of UTMI+, this is very similar to the existing Exynos850
support in this driver. The difference is that it supports both UTMI+
(HS) and PIPE3 (SS). Firstly, there are some preparatory patches to convert
this driver to using the clk_bulk and regulator_bulk APIs to simplify
addition, while the bulk of the changes is around the SS part.

Dependencies on other patches:
While there is no compile or link time dependency, for USB to actually work
this series also requires Peter's syscon changes from
https://lore.kernel.org/all/[e-mail]/

To: Vinod Koul <[e-mail]>
To: Kishon Vijay Abraham I <[e-mail]>
To: Rob Herring <[e-mail]>
To: Krzysztof Kozlowski <[e-mail]>
To: Conor Dooley <[e-mail]>
To: Peter Griffin <[e-mail]>
To: Marek Szyprowski <[e-mail]>
To: Sylwester Nawrocki <[e-mail]>
To: Alim Akhtar <[e-mail]>
To: Sam Protsenko <[e-mail]>
Cc: Krzysztof Kozlowski <[e-mail]>
Cc: Tudor Ambarus <[e-mail]>
Cc: Will McVicker <[e-mail]>
Cc: Roy Luo <[e-mail]>
Cc: [e-mail]
Cc: [e-mail]
Cc: [e-mail]
Cc: [e-mail]
Cc: [e-mail]
Cc: [e-mail]
Signed-off-by: André Draszik <[e-mail]>

Changes in v3:
- drop patch 'phy: exynos5-usbdrd: use exynos_get_pmu_regmap_by_phandle()
  for PMU regs'. This is not needed anymore with Peter's syscon series
  mentioned above (Krzysztof).
- drop those patches that have already been merged via
  https://lore.kernel.org/all/[e-mail]/
- update device tree binding 'reg-names' (Krzysztof)
- use clk_bulk and regulator_bulk APIs throughout to simplify addition of
  gs101 support as preparatory patches
- patch 1: add required but missing regulators
- patch 4:
    * make the register access clock name(s) platform specific and avoid
      use of devm_clk_bulk_get_optional() as we want to be sure to have
      retrieved all required clocks
    * fix a whitespace issue
    * slightly rephrase commit message
- patch 6:
    * set unused callback pointers to NULL in gs101_tunes[]
    * implement missing regulator support and enable power to phy before any
      register access
    * add more phy tunes
    * move PTS_UTMI_POSTINIT utmi phy tuning to before completion of POR
      sequence, as per datasheet
    * group gs101 related symbols closer to each other 
- Link to v2: https://lore.kernel.org/r/[e-mail]

Changes in v2:
- avoid having nested else/if in the DT binding (Rob)
- add missing bitfield.h include
- Link to v1: https://lore.kernel.org/r/[e-mail]

---
André Draszik (6):
      dt-bindings: phy: samsung,usb3-drd-phy: add gs101 compatible
      phy: exynos5-usbdrd: support isolating HS and SS ports independently
      phy: exynos5-usbdrd: convert core clocks to clk_bulk
      phy: exynos5-usbdrd: convert (phy) register access clock to clk_bulk
      phy: exynos5-usbdrd: convert Vbus supplies to regulator_bulk
      phy: exynos5-usbdrd: support Exynos USBDRD 3.1 combo phy (HS & SS)

 .../bindings/phy/samsung,usb3-drd-phy.yaml         |  77 +-
 drivers/phy/samsung/phy-exynos5-usbdrd.c           | 958 +++++++++++++++++----
 include/linux/soc/samsung/exynos-regs-pmu.h        |   4 +
 3 files changed, 893 insertions(+), 146 deletions(-)
---
base-commit: 6906a84c482f098d31486df8dc98cead21cce2d0
change-id: 20240423-usb-phy-gs101-abf3e172d1c4

Best regards,

Comments

William McVicker June 22, 2024, 12:24 a.m. UTC | #1

On 06/17/2024, André Draszik wrote:
> This patch series adds support for the Exynos USB 3.1 DRD combo phy, as
> found in Exynos 9 SoCs like Google GS101. It supports USB SS, HS and
> DisplayPort, but DisplayPort is out of scope for this series.
> 
> In terms of UTMI+, this is very similar to the existing Exynos850
> support in this driver. The difference is that it supports both UTMI+
> (HS) and PIPE3 (SS). Firstly, there are some preparatory patches to convert
> this driver to using the clk_bulk and regulator_bulk APIs to simplify
> addition, while the bulk of the changes is around the SS part.
> 
> Dependencies on other patches:
> While there is no compile or link time dependency, for USB to actually work
> this series also requires Peter's syscon changes from
> https://lore.kernel.org/all/[e-mail]/
> 
> To: Vinod Koul <[e-mail]>
> To: Kishon Vijay Abraham I <[e-mail]>
> To: Rob Herring <[e-mail]>
> To: Krzysztof Kozlowski <[e-mail]>
> To: Conor Dooley <[e-mail]>
> To: Peter Griffin <[e-mail]>
> To: Marek Szyprowski <[e-mail]>
> To: Sylwester Nawrocki <[e-mail]>
> To: Alim Akhtar <[e-mail]>
> To: Sam Protsenko <[e-mail]>
> Cc: Krzysztof Kozlowski <[e-mail]>
> Cc: Tudor Ambarus <[e-mail]>
> Cc: Will McVicker <[e-mail]>
> Cc: Roy Luo <[e-mail]>
> Cc: [e-mail]
> Cc: [e-mail]
> Cc: [e-mail]
> Cc: [e-mail]
> Cc: [e-mail]
> Cc: [e-mail]
> Signed-off-by: André Draszik <[e-mail]>
> 
> Changes in v3:
> - drop patch 'phy: exynos5-usbdrd: use exynos_get_pmu_regmap_by_phandle()
>   for PMU regs'. This is not needed anymore with Peter's syscon series
>   mentioned above (Krzysztof).
> - drop those patches that have already been merged via
>   https://lore.kernel.org/all/[e-mail]/
> - update device tree binding 'reg-names' (Krzysztof)
> - use clk_bulk and regulator_bulk APIs throughout to simplify addition of
>   gs101 support as preparatory patches
> - patch 1: add required but missing regulators
> - patch 4:
>     * make the register access clock name(s) platform specific and avoid
>       use of devm_clk_bulk_get_optional() as we want to be sure to have
>       retrieved all required clocks
>     * fix a whitespace issue
>     * slightly rephrase commit message
> - patch 6:
>     * set unused callback pointers to NULL in gs101_tunes[]
>     * implement missing regulator support and enable power to phy before any
>       register access
>     * add more phy tunes
>     * move PTS_UTMI_POSTINIT utmi phy tuning to before completion of POR
>       sequence, as per datasheet
>     * group gs101 related symbols closer to each other 
> - Link to v2: https://lore.kernel.org/r/[e-mail]
> 
> Changes in v2:
> - avoid having nested else/if in the DT binding (Rob)
> - add missing bitfield.h include
> - Link to v1: https://lore.kernel.org/r/[e-mail]
> 
> ---
> André Draszik (6):
>       dt-bindings: phy: samsung,usb3-drd-phy: add gs101 compatible
>       phy: exynos5-usbdrd: support isolating HS and SS ports independently
>       phy: exynos5-usbdrd: convert core clocks to clk_bulk
>       phy: exynos5-usbdrd: convert (phy) register access clock to clk_bulk
>       phy: exynos5-usbdrd: convert Vbus supplies to regulator_bulk
>       phy: exynos5-usbdrd: support Exynos USBDRD 3.1 combo phy (HS & SS)
> 
>  .../bindings/phy/samsung,usb3-drd-phy.yaml         |  77 +-
>  drivers/phy/samsung/phy-exynos5-usbdrd.c           | 958 +++++++++++++++++----
>  include/linux/soc/samsung/exynos-regs-pmu.h        |   4 +
>  3 files changed, 893 insertions(+), 146 deletions(-)
> ---
> base-commit: 6906a84c482f098d31486df8dc98cead21cce2d0
> change-id: 20240423-usb-phy-gs101-abf3e172d1c4
> 
> Best regards,
> -- 
> André Draszik <[e-mail]>
> 

Thanks Andre! I tested this out on my Pixel 6 Pro. I verified the USB modules
load and probe as expected. I also verified my device is detected via adb on my
host machine. However, occasionally when I boot from RAM the device doesn't
come up via adb compared to when I flash and run `fastboot reboot`. So there
must be something happening differently when booting from fastboot mode versus
a reboot. Specifically, when I flash the kernel and run `fastboot reboot`, adb
has always come up, but booting the kernel from RAM results in about 30% adb
detection fail rate. I'll keep an eye on this.

$ adb shell lsmod
Module                  Size  Used by
at24                   24576  0
dwc3_exynos            12288  0
i2c_exynos5            28672  0
ufs_exynos             32768  0
phy_exynos_ufs         20480  1
phy_exynos5_usbdrd     36864  2
s3c2410_wdt            24576  0
arm_dsu_pmu            24576  0

Thanks,
Will

Vinod Koul July 2, 2024, 1:36 p.m. UTC | #2

On Mon, 17 Jun 2024 17:44:41 +0100, André Draszik wrote:
> This patch series adds support for the Exynos USB 3.1 DRD combo phy, as
> found in Exynos 9 SoCs like Google GS101. It supports USB SS, HS and
> DisplayPort, but DisplayPort is out of scope for this series.
> 
> In terms of UTMI+, this is very similar to the existing Exynos850
> support in this driver. The difference is that it supports both UTMI+
> (HS) and PIPE3 (SS). Firstly, there are some preparatory patches to convert
> this driver to using the clk_bulk and regulator_bulk APIs to simplify
> addition, while the bulk of the changes is around the SS part.
> 
> [...]

Applied, thanks!

[1/6] dt-bindings: phy: samsung,usb3-drd-phy: add gs101 compatible
      commit: e340c041b7a4c0321bfe2cb54817837c9040c739
[2/6] phy: exynos5-usbdrd: support isolating HS and SS ports independently
      commit: bbb28a1d733a94330f5778b4cd0dbccf6c34597d
[3/6] phy: exynos5-usbdrd: convert core clocks to clk_bulk
      commit: 54290bd9811ecdd82c19b96093e2c78325f59574
[4/6] phy: exynos5-usbdrd: convert (phy) register access clock to clk_bulk
      commit: 26ba3261215b44d466bd2093daf3796031c09c0a
[5/6] phy: exynos5-usbdrd: convert Vbus supplies to regulator_bulk
      commit: 497ddafe915e8d9fb4d11542d16a1ff95a3e8034
[6/6] phy: exynos5-usbdrd: support Exynos USBDRD 3.1 combo phy (HS & SS)
      commit: 32267c29bc7d5c9654b71e4f354064217a5fb053

Best regards,