| Message ID | 20240613071327.2498953-7-luchangqi.123@bytedance.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Support persistent reservation operations | expand |
On Thu, Jun 13, 2024 at 03:13:23PM +0800, Changqi Lu wrote: > Add constants for the NVMe persistent command protocol. > The constants include the reservation command opcode and > reservation type values defined in section 7 of the NVMe > 2.0 specification. > > Signed-off-by: Changqi Lu <luchangqi.123@bytedance.com> > Signed-off-by: zhenwei pi <pizhenwei@bytedance.com> > --- > include/block/nvme.h | 61 ++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 61 insertions(+) > > diff --git a/include/block/nvme.h b/include/block/nvme.h > index bb231d0b9a..da6ccb0f3b 100644 > --- a/include/block/nvme.h > +++ b/include/block/nvme.h > @@ -633,6 +633,10 @@ enum NvmeIoCommands { > NVME_CMD_WRITE_ZEROES = 0x08, > NVME_CMD_DSM = 0x09, > NVME_CMD_VERIFY = 0x0c, > + NVME_CMD_RESV_REGISTER = 0x0d, > + NVME_CMD_RESV_REPORT = 0x0e, > + NVME_CMD_RESV_ACQUIRE = 0x11, > + NVME_CMD_RESV_RELEASE = 0x15, > NVME_CMD_IO_MGMT_RECV = 0x12, Keep NVME_CMD_IO_MGMT_RECV (0x12) before NVME_CMD_RESV_RELEASE (0x15) in sorted order? > NVME_CMD_COPY = 0x19, > NVME_CMD_IO_MGMT_SEND = 0x1d, > @@ -641,6 +645,63 @@ enum NvmeIoCommands { > NVME_CMD_ZONE_APPEND = 0x7d, > }; > > +typedef enum { > + NVME_RESV_REGISTER_ACTION_REGISTER = 0x00, > + NVME_RESV_REGISTER_ACTION_UNREGISTER = 0x01, > + NVME_RESV_REGISTER_ACTION_REPLACE = 0x02, > +} NvmeReservationRegisterAction; > + > +typedef enum { > + NVME_RESV_RELEASE_ACTION_RELEASE = 0x00, > + NVME_RESV_RELEASE_ACTION_CLEAR = 0x01, > +} NvmeReservationReleaseAction; > + > +typedef enum { > + NVME_RESV_ACQUIRE_ACTION_ACQUIRE = 0x00, > + NVME_RESV_ACQUIRE_ACTION_PREEMPT = 0x01, > + NVME_RESV_ACQUIRE_ACTION_PREEMPT_AND_ABORT = 0x02, > +} NvmeReservationAcquireAction; > + > +typedef enum { > + NVME_RESV_WRITE_EXCLUSIVE = 0x01, > + NVME_RESV_EXCLUSIVE_ACCESS = 0x02, > + NVME_RESV_WRITE_EXCLUSIVE_REGS_ONLY = 0x03, > + NVME_RESV_EXCLUSIVE_ACCESS_REGS_ONLY = 0x04, > + NVME_RESV_WRITE_EXCLUSIVE_ALL_REGS = 0x05, > + NVME_RESV_EXCLUSIVE_ACCESS_ALL_REGS = 0x06, > +} NvmeResvType; > + > +typedef enum { > + NVME_RESV_PTPL_NO_CHANGE = 0x00, > + NVME_RESV_PTPL_DISABLE = 0x02, > + NVME_RESV_PTPL_ENABLE = 0x03, > +} NvmeResvPTPL; > + > +typedef enum NVMEPrCap { > + /* Persist Through Power Loss */ > + NVME_PR_CAP_PTPL = 1 << 0, > + /* Write Exclusive reservation type */ > + NVME_PR_CAP_WR_EX = 1 << 1, > + /* Exclusive Access reservation type */ > + NVME_PR_CAP_EX_AC = 1 << 2, > + /* Write Exclusive Registrants Only reservation type */ > + NVME_PR_CAP_WR_EX_RO = 1 << 3, > + /* Exclusive Access Registrants Only reservation type */ > + NVME_PR_CAP_EX_AC_RO = 1 << 4, > + /* Write Exclusive All Registrants reservation type */ > + NVME_PR_CAP_WR_EX_AR = 1 << 5, > + /* Exclusive Access All Registrants reservation type */ > + NVME_PR_CAP_EX_AC_AR = 1 << 6, > + > + NVME_PR_CAP_ALL = (NVME_PR_CAP_PTPL | > + NVME_PR_CAP_WR_EX | > + NVME_PR_CAP_EX_AC | > + NVME_PR_CAP_WR_EX_RO | > + NVME_PR_CAP_EX_AC_RO | > + NVME_PR_CAP_WR_EX_AR | > + NVME_PR_CAP_EX_AC_AR), > +} NvmePrCap; > + > typedef struct QEMU_PACKED NvmeDeleteQ { > uint8_t opcode; > uint8_t flags; > -- > 2.20.1 >
diff --git a/include/block/nvme.h b/include/block/nvme.h index bb231d0b9a..da6ccb0f3b 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -633,6 +633,10 @@ enum NvmeIoCommands { NVME_CMD_WRITE_ZEROES = 0x08, NVME_CMD_DSM = 0x09, NVME_CMD_VERIFY = 0x0c, + NVME_CMD_RESV_REGISTER = 0x0d, + NVME_CMD_RESV_REPORT = 0x0e, + NVME_CMD_RESV_ACQUIRE = 0x11, + NVME_CMD_RESV_RELEASE = 0x15, NVME_CMD_IO_MGMT_RECV = 0x12, NVME_CMD_COPY = 0x19, NVME_CMD_IO_MGMT_SEND = 0x1d, @@ -641,6 +645,63 @@ enum NvmeIoCommands { NVME_CMD_ZONE_APPEND = 0x7d, }; +typedef enum { + NVME_RESV_REGISTER_ACTION_REGISTER = 0x00, + NVME_RESV_REGISTER_ACTION_UNREGISTER = 0x01, + NVME_RESV_REGISTER_ACTION_REPLACE = 0x02, +} NvmeReservationRegisterAction; + +typedef enum { + NVME_RESV_RELEASE_ACTION_RELEASE = 0x00, + NVME_RESV_RELEASE_ACTION_CLEAR = 0x01, +} NvmeReservationReleaseAction; + +typedef enum { + NVME_RESV_ACQUIRE_ACTION_ACQUIRE = 0x00, + NVME_RESV_ACQUIRE_ACTION_PREEMPT = 0x01, + NVME_RESV_ACQUIRE_ACTION_PREEMPT_AND_ABORT = 0x02, +} NvmeReservationAcquireAction; + +typedef enum { + NVME_RESV_WRITE_EXCLUSIVE = 0x01, + NVME_RESV_EXCLUSIVE_ACCESS = 0x02, + NVME_RESV_WRITE_EXCLUSIVE_REGS_ONLY = 0x03, + NVME_RESV_EXCLUSIVE_ACCESS_REGS_ONLY = 0x04, + NVME_RESV_WRITE_EXCLUSIVE_ALL_REGS = 0x05, + NVME_RESV_EXCLUSIVE_ACCESS_ALL_REGS = 0x06, +} NvmeResvType; + +typedef enum { + NVME_RESV_PTPL_NO_CHANGE = 0x00, + NVME_RESV_PTPL_DISABLE = 0x02, + NVME_RESV_PTPL_ENABLE = 0x03, +} NvmeResvPTPL; + +typedef enum NVMEPrCap { + /* Persist Through Power Loss */ + NVME_PR_CAP_PTPL = 1 << 0, + /* Write Exclusive reservation type */ + NVME_PR_CAP_WR_EX = 1 << 1, + /* Exclusive Access reservation type */ + NVME_PR_CAP_EX_AC = 1 << 2, + /* Write Exclusive Registrants Only reservation type */ + NVME_PR_CAP_WR_EX_RO = 1 << 3, + /* Exclusive Access Registrants Only reservation type */ + NVME_PR_CAP_EX_AC_RO = 1 << 4, + /* Write Exclusive All Registrants reservation type */ + NVME_PR_CAP_WR_EX_AR = 1 << 5, + /* Exclusive Access All Registrants reservation type */ + NVME_PR_CAP_EX_AC_AR = 1 << 6, + + NVME_PR_CAP_ALL = (NVME_PR_CAP_PTPL | + NVME_PR_CAP_WR_EX | + NVME_PR_CAP_EX_AC | + NVME_PR_CAP_WR_EX_RO | + NVME_PR_CAP_EX_AC_RO | + NVME_PR_CAP_WR_EX_AR | + NVME_PR_CAP_EX_AC_AR), +} NvmePrCap; + typedef struct QEMU_PACKED NvmeDeleteQ { uint8_t opcode; uint8_t flags;