| Message ID | 20240704-add-mtk-isp-3-0-support-v5-1-bfccccc5ec21@baylibre.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add Mediatek ISP3.0 | expand |
On Thu, Jul 04, 2024 at 03:36:40PM +0200, Julien Stephan wrote: > From: Louis Kuo <louis.kuo@mediatek.com> > > This adds the bindings, for the mediatek ISP3.0 SENINF module embedded in > some Mediatek SoC, such as the mt8365 > > Signed-off-by: Louis Kuo <louis.kuo@mediatek.com> > Signed-off-by: Phi-Bang Nguyen <pnguyen@baylibre.com> > Link: https://lore.kernel.org/r/20230807094940.329165-2-jstephan@baylibre.com > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > Signed-off-by: Julien Stephan <jstephan@baylibre.com> I'm really confused by the link tag here. At first glance this looked like you were sending out something that had been applied by Laurent, given the Link, Rb and SoB from him. Why does he have a SoB on this patch? What did Phi-Bang Nguyen do with this patch, and should they have a Co-developed-by tag? > --- > .../bindings/media/mediatek,mt8365-seninf.yaml | 275 +++++++++++++++++++++ > MAINTAINERS | 7 + > 2 files changed, 282 insertions(+) > > diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml > new file mode 100644 > index 000000000000..aeabea9f956a > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml > @@ -0,0 +1,275 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (c) 2023 MediaTek, BayLibre > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/mediatek,mt8365-seninf.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek Sensor Interface 3.0 > + > +maintainers: > + - Laurent Pinchart <laurent.pinchart@ideasonboard.com> > + - Julien Stephan <jstephan@baylibre.com> > + - Andy Hsieh <andy.hsieh@mediatek.com> > + > +description: > + The ISP3.0 SENINF is the CSI-2 and parallel camera sensor interface found in > + multiple MediaTek SoCs. It can support up to three physical CSI-2 input ports, > + configured in DPHY (2 or 4 data lanes) or CPHY depending on the SoC. > + On the output side, SENINF can be connected either to CAMSV instance or > + to the internal ISP. CAMSV is used to bypass the internal ISP processing > + in order to connect either an external ISP, or a sensor (RAW, YUV). > + > +properties: > + compatible: > + const: mediatek,mt8365-seninf > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + clocks: > + items: > + - description: Seninf camsys clock > + - description: Seninf top mux clock > + > + clock-names: > + items: > + - const: camsys > + - const: top_mux > + > + phys: true > + > + phy-names: true > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: CSI0 or CSI0A port > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + clock-lanes: > + maxItems: 1 > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + port@1: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: CSI1 port > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + clock-lanes: > + maxItems: 1 > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + port@2: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: CSI2 port > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + clock-lanes: > + maxItems: 1 > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + port@3: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: CSI0B port > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + clock-lanes: > + maxItems: 1 > + data-lanes: > + minItems: 1 > + maxItems: 2 > + > + port@4: > + $ref: /schemas/graph.yaml#/properties/port > + description: connection point for cam0 > + > + port@5: > + $ref: /schemas/graph.yaml#/properties/port > + description: connection point for cam1 > + > + port@6: > + $ref: /schemas/graph.yaml#/properties/port > + description: connection point for camsv0 > + > + port@7: > + $ref: /schemas/graph.yaml#/properties/port > + description: connection point for camsv1 > + > + port@8: > + $ref: /schemas/graph.yaml#/properties/port > + description: connection point for camsv2 > + > + port@9: > + $ref: /schemas/graph.yaml#/properties/port > + description: connection point for camsv3 > + > + required: > + - port@0 > + - port@1 > + - port@2 > + - port@3 > + - port@4 > + - port@5 > + - port@6 > + - port@7 > + - port@8 > + - port@9 > + > +required: > + - compatible > + - interrupts > + - clocks > + - clock-names > + - power-domains > + - ports > + > +additionalProperties: false > + > +if: > + properties: > + compatible: > + contains: > + const: mediatek,mt8365-seninf The binding supports only a single compatible, why is this complexity required? I don't see other devices being added in this series. Cheers, Conor. > +then: > + properties: > + phys: > + minItems: 2 > + maxItems: 2 > + description: > + phandle to the PHYs connected to CSI0/A, CSI1, CSI0B > + > + phy-names: > + description: > + list of PHYs names > + minItems: 2 > + maxItems: 2 > + items: > + type: string > + enum: > + - csi0 > + - csi1 > + - csi0b > + uniqueItems: true
Le jeu. 4 juil. 2024 à 18:27, Conor Dooley <conor@kernel.org> a écrit : > > On Thu, Jul 04, 2024 at 03:36:40PM +0200, Julien Stephan wrote: > > From: Louis Kuo <louis.kuo@mediatek.com> > > > > This adds the bindings, for the mediatek ISP3.0 SENINF module embedded in > > some Mediatek SoC, such as the mt8365 > > > > Signed-off-by: Louis Kuo <louis.kuo@mediatek.com> > > Signed-off-by: Phi-Bang Nguyen <pnguyen@baylibre.com> > > Link: https://lore.kernel.org/r/20230807094940.329165-2-jstephan@baylibre.com > > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > > Signed-off-by: Julien Stephan <jstephan@baylibre.com> > > I'm really confused by the link tag here. At first glance this looked > like you were sending out something that had been applied by Laurent, > given the Link, Rb and SoB from him. Why does he have a SoB on this > patch? What did Phi-Bang Nguyen do with this patch, and should they have > a Co-developed-by tag? Hi Conor, I was not using b4 for the previous revisions of this series, so maybe I messed something up here :( About Phi-Bang, this series has been in our internal tree for a long time, and Phi-Bang has his SoB on it, so I kept it. About Laurent's tags, they were already on v4. But maybe it was an error ? Should I remove them? > > > --- > > .../bindings/media/mediatek,mt8365-seninf.yaml | 275 +++++++++++++++++++++ > > MAINTAINERS | 7 + > > 2 files changed, 282 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml > > new file mode 100644 > > index 000000000000..aeabea9f956a > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml > > @@ -0,0 +1,275 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +# Copyright (c) 2023 MediaTek, BayLibre > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/media/mediatek,mt8365-seninf.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: MediaTek Sensor Interface 3.0 > > + > > +maintainers: > > + - Laurent Pinchart <laurent.pinchart@ideasonboard.com> > > + - Julien Stephan <jstephan@baylibre.com> > > + - Andy Hsieh <andy.hsieh@mediatek.com> > > + > > +description: > > + The ISP3.0 SENINF is the CSI-2 and parallel camera sensor interface found in > > + multiple MediaTek SoCs. It can support up to three physical CSI-2 input ports, > > + configured in DPHY (2 or 4 data lanes) or CPHY depending on the SoC. > > + On the output side, SENINF can be connected either to CAMSV instance or > > + to the internal ISP. CAMSV is used to bypass the internal ISP processing > > + in order to connect either an external ISP, or a sensor (RAW, YUV). > > + > > +properties: > > + compatible: > > + const: mediatek,mt8365-seninf > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 1 > > + > > + power-domains: > > + maxItems: 1 > > + > > + clocks: > > + items: > > + - description: Seninf camsys clock > > + - description: Seninf top mux clock > > + > > + clock-names: > > + items: > > + - const: camsys > > + - const: top_mux > > + > > + phys: true > > + > > + phy-names: true > > + > > + ports: > > + $ref: /schemas/graph.yaml#/properties/ports > > + > > + properties: > > + port@0: > > + $ref: /schemas/graph.yaml#/$defs/port-base > > + unevaluatedProperties: false > > + description: CSI0 or CSI0A port > > + > > + properties: > > + endpoint: > > + $ref: video-interfaces.yaml# > > + unevaluatedProperties: false > > + > > + properties: > > + clock-lanes: > > + maxItems: 1 > > + data-lanes: > > + minItems: 1 > > + maxItems: 4 > > + > > + port@1: > > + $ref: /schemas/graph.yaml#/$defs/port-base > > + unevaluatedProperties: false > > + description: CSI1 port > > + > > + properties: > > + endpoint: > > + $ref: video-interfaces.yaml# > > + unevaluatedProperties: false > > + > > + properties: > > + clock-lanes: > > + maxItems: 1 > > + data-lanes: > > + minItems: 1 > > + maxItems: 4 > > + > > + port@2: > > + $ref: /schemas/graph.yaml#/$defs/port-base > > + unevaluatedProperties: false > > + description: CSI2 port > > + > > + properties: > > + endpoint: > > + $ref: video-interfaces.yaml# > > + unevaluatedProperties: false > > + > > + properties: > > + clock-lanes: > > + maxItems: 1 > > + data-lanes: > > + minItems: 1 > > + maxItems: 4 > > + > > + port@3: > > + $ref: /schemas/graph.yaml#/$defs/port-base > > + unevaluatedProperties: false > > + description: CSI0B port > > + > > + properties: > > + endpoint: > > + $ref: video-interfaces.yaml# > > + unevaluatedProperties: false > > + > > + properties: > > + clock-lanes: > > + maxItems: 1 > > + data-lanes: > > + minItems: 1 > > + maxItems: 2 > > + > > + port@4: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: connection point for cam0 > > + > > + port@5: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: connection point for cam1 > > + > > + port@6: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: connection point for camsv0 > > + > > + port@7: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: connection point for camsv1 > > + > > + port@8: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: connection point for camsv2 > > + > > + port@9: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: connection point for camsv3 > > + > > + required: > > + - port@0 > > + - port@1 > > + - port@2 > > + - port@3 > > + - port@4 > > + - port@5 > > + - port@6 > > + - port@7 > > + - port@8 > > + - port@9 > > + > > +required: > > + - compatible > > + - interrupts > > + - clocks > > + - clock-names > > + - power-domains > > + - ports > > + > > +additionalProperties: false > > + > > +if: > > + properties: > > + compatible: > > + contains: > > + const: mediatek,mt8365-seninf > > The binding supports only a single compatible, why is this complexity > required? I don't see other devices being added in this series. Right. The idea is that the number of PHYs depends on the SoC. In the previous revision of the series, the number of PHYs was not fixed, and Krzysztof asked me to fix it by SoC. So I wanted to make it clear that the number of PHYs depends on SoC but maybe I don't need that complexity for that? Is something like the following enough? And if complexity is added later if some other SoC are added? phys: minItems: 2 maxItems: 2 description: phandle to the PHYs connected to CSI0/A, CSI1, CSI0B phy-names: description: list of PHYs names minItems: 2 maxItems: 2 items: type: string enum: - csi0 - csi1 - csi0b uniqueItems: true Cheers Julien > > Cheers, > Conor. > > > +then: > > + properties: > > + phys: > > + minItems: 2 > > + maxItems: 2 > > + description: > > + phandle to the PHYs connected to CSI0/A, CSI1, CSI0B > > + > > + phy-names: > > + description: > > + list of PHYs names > > + minItems: 2 > > + maxItems: 2 > > + items: > > + type: string > > + enum: > > + - csi0 > > + - csi1 > > + - csi0b > > + uniqueItems: true
On Fri, Jul 05, 2024 at 09:50:59AM +0200, Julien Stephan wrote: > Le jeu. 4 juil. 2024 à 18:27, Conor Dooley <conor@kernel.org> a écrit : > > > > On Thu, Jul 04, 2024 at 03:36:40PM +0200, Julien Stephan wrote: > > > From: Louis Kuo <louis.kuo@mediatek.com> > > > > > > This adds the bindings, for the mediatek ISP3.0 SENINF module embedded in > > > some Mediatek SoC, such as the mt8365 > > > > > > Signed-off-by: Louis Kuo <louis.kuo@mediatek.com> > > > Signed-off-by: Phi-Bang Nguyen <pnguyen@baylibre.com> > > > Link: https://lore.kernel.org/r/20230807094940.329165-2-jstephan@baylibre.com > > > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > > > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > > > Signed-off-by: Julien Stephan <jstephan@baylibre.com> > > > > I'm really confused by the link tag here. At first glance this looked > > like you were sending out something that had been applied by Laurent, > > given the Link, Rb and SoB from him. Why does he have a SoB on this > > patch? What did Phi-Bang Nguyen do with this patch, and should they have > > a Co-developed-by tag? > > I was not using b4 for the previous revisions of this series, so maybe > I messed something up here :( b4 am has an option to add a link to a patch you apply from the mailing list (-l, --add-link) but you should not be using that as a contributor. In this case, that link provides no value and is just confusing. > About Phi-Bang, this series has been in our internal tree for a long > time, and Phi-Bang has his SoB on it, so I kept it. > > About Laurent's tags, they were already on v4. But maybe it was an > error ? Should I remove them? They were also on v1. Did Laurent write part of these bindings, and should he have a Co-developed-by? > > > +additionalProperties: false > > > + > > > +if: > > > + properties: > > > + compatible: > > > + contains: > > > + const: mediatek,mt8365-seninf > > > > The binding supports only a single compatible, why is this complexity > > required? I don't see other devices being added in this series. > > Right. The idea is that the number of PHYs depends on the SoC. In the > previous revision of the series, > the number of PHYs was not fixed, and Krzysztof asked me to fix it by > SoC. So I wanted to make it clear > that the number of PHYs depends on SoC but maybe I don't need that > complexity for that? > > Is something like the following enough? And if complexity is added > later if some other SoC are added? Yes, that looks reasonable to me. Adding conditional stuff can be done iff another soc re-uses the binding. Thanks, Conor. > phys: > minItems: 2 > maxItems: 2 > description: > phandle to the PHYs connected to CSI0/A, CSI1, CSI0B > > phy-names: > description: > list of PHYs names > minItems: 2 > maxItems: 2 > items: > type: string > enum: > - csi0 > - csi1 > - csi0b > uniqueItems: true
Le ven. 5 juil. 2024 à 11:24, Conor Dooley <conor.dooley@microchip.com> a écrit : > > On Fri, Jul 05, 2024 at 09:50:59AM +0200, Julien Stephan wrote: > > Le jeu. 4 juil. 2024 à 18:27, Conor Dooley <conor@kernel.org> a écrit : > > > > > > On Thu, Jul 04, 2024 at 03:36:40PM +0200, Julien Stephan wrote: > > > > From: Louis Kuo <louis.kuo@mediatek.com> > > > > > > > > This adds the bindings, for the mediatek ISP3.0 SENINF module embedded in > > > > some Mediatek SoC, such as the mt8365 > > > > > > > > Signed-off-by: Louis Kuo <louis.kuo@mediatek.com> > > > > Signed-off-by: Phi-Bang Nguyen <pnguyen@baylibre.com> > > > > Link: https://lore.kernel.org/r/20230807094940.329165-2-jstephan@baylibre.com > > > > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > > > > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > > > > Signed-off-by: Julien Stephan <jstephan@baylibre.com> > > > > > > I'm really confused by the link tag here. At first glance this looked > > > like you were sending out something that had been applied by Laurent, > > > given the Link, Rb and SoB from him. Why does he have a SoB on this > > > patch? What did Phi-Bang Nguyen do with this patch, and should they have > > > a Co-developed-by tag? > > > > I was not using b4 for the previous revisions of this series, so maybe > > I messed something up here :( > > b4 am has an option to add a link to a patch you apply from the mailing > list (-l, --add-link) but you should not be using that as a contributor. > In this case, that link provides no value and is just confusing. > > > About Phi-Bang, this series has been in our internal tree for a long > > time, and Phi-Bang has his SoB on it, so I kept it. > > > > About Laurent's tags, they were already on v4. But maybe it was an > > error ? Should I remove them? > > They were also on v1. Did Laurent write part of these bindings, and > should he have a Co-developed-by? > Got it! I understood where I messed up :) I'll remove the link and add the Co-developed-by tag of Laurent > > > > +additionalProperties: false > > > > + > > > > +if: > > > > + properties: > > > > + compatible: > > > > + contains: > > > > + const: mediatek,mt8365-seninf > > > > > > The binding supports only a single compatible, why is this complexity > > > required? I don't see other devices being added in this series. > > > > Right. The idea is that the number of PHYs depends on the SoC. In the > > previous revision of the series, > > the number of PHYs was not fixed, and Krzysztof asked me to fix it by > > SoC. So I wanted to make it clear > > that the number of PHYs depends on SoC but maybe I don't need that > > complexity for that? > > > > Is something like the following enough? And if complexity is added > > later if some other SoC are added? > > Yes, that looks reasonable to me. Adding conditional stuff can be done > iff another soc re-uses the binding. Will do in the next series. Thank you for your feedback on this! Cheers Julien > > Thanks, > Conor. > > > phys: > > minItems: 2 > > maxItems: 2 > > description: > > phandle to the PHYs connected to CSI0/A, CSI1, CSI0B > > > > phy-names: > > description: > > list of PHYs names > > minItems: 2 > > maxItems: 2 > > items: > > type: string > > enum: > > - csi0 > > - csi1 > > - csi0b > > uniqueItems: true
diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml new file mode 100644 index 000000000000..aeabea9f956a --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml @@ -0,0 +1,275 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2023 MediaTek, BayLibre +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mt8365-seninf.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Sensor Interface 3.0 + +maintainers: + - Laurent Pinchart <laurent.pinchart@ideasonboard.com> + - Julien Stephan <jstephan@baylibre.com> + - Andy Hsieh <andy.hsieh@mediatek.com> + +description: + The ISP3.0 SENINF is the CSI-2 and parallel camera sensor interface found in + multiple MediaTek SoCs. It can support up to three physical CSI-2 input ports, + configured in DPHY (2 or 4 data lanes) or CPHY depending on the SoC. + On the output side, SENINF can be connected either to CAMSV instance or + to the internal ISP. CAMSV is used to bypass the internal ISP processing + in order to connect either an external ISP, or a sensor (RAW, YUV). + +properties: + compatible: + const: mediatek,mt8365-seninf + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + items: + - description: Seninf camsys clock + - description: Seninf top mux clock + + clock-names: + items: + - const: camsys + - const: top_mux + + phys: true + + phy-names: true + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: CSI0 or CSI0A port + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + data-lanes: + minItems: 1 + maxItems: 4 + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: CSI1 port + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + data-lanes: + minItems: 1 + maxItems: 4 + + port@2: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: CSI2 port + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + data-lanes: + minItems: 1 + maxItems: 4 + + port@3: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: CSI0B port + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + data-lanes: + minItems: 1 + maxItems: 2 + + port@4: + $ref: /schemas/graph.yaml#/properties/port + description: connection point for cam0 + + port@5: + $ref: /schemas/graph.yaml#/properties/port + description: connection point for cam1 + + port@6: + $ref: /schemas/graph.yaml#/properties/port + description: connection point for camsv0 + + port@7: + $ref: /schemas/graph.yaml#/properties/port + description: connection point for camsv1 + + port@8: + $ref: /schemas/graph.yaml#/properties/port + description: connection point for camsv2 + + port@9: + $ref: /schemas/graph.yaml#/properties/port + description: connection point for camsv3 + + required: + - port@0 + - port@1 + - port@2 + - port@3 + - port@4 + - port@5 + - port@6 + - port@7 + - port@8 + - port@9 + +required: + - compatible + - interrupts + - clocks + - clock-names + - power-domains + - ports + +additionalProperties: false + +if: + properties: + compatible: + contains: + const: mediatek,mt8365-seninf +then: + properties: + phys: + minItems: 2 + maxItems: 2 + description: + phandle to the PHYs connected to CSI0/A, CSI1, CSI0B + + phy-names: + description: + list of PHYs names + minItems: 2 + maxItems: 2 + items: + type: string + enum: + - csi0 + - csi1 + - csi0b + uniqueItems: true + +examples: + - | + #include <dt-bindings/clock/mediatek,mt8365-clk.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/phy/phy.h> + #include <dt-bindings/power/mediatek,mt8365-power.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + csi: csi@15040000 { + compatible = "mediatek,mt8365-seninf"; + reg = <0 0x15040000 0 0x6000>; + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_LOW>; + clocks = <&camsys CLK_CAM_SENIF>, + <&topckgen CLK_TOP_SENIF_SEL>; + clock-names = "camsys", "top_mux"; + + power-domains = <&spm MT8365_POWER_DOMAIN_CAM>; + + phys = <&mipi_csi0 PHY_TYPE_DPHY>, <&mipi_csi1>; + phy-names = "csi0", "csi1"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + seninf_in1: endpoint { + clock-lanes = <2>; + data-lanes = <1 3 0 4>; + remote-endpoint = <&isp1_out>; + }; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + + port@4 { + reg = <4>; + seninf_camsv1_endpoint: endpoint { + remote-endpoint = <&camsv1_endpoint>; + }; + }; + + port@5 { + reg = <5>; + seninf_camsv2_endpoint: endpoint { + remote-endpoint = <&camsv2_endpoint>; + }; + }; + + port@6 { + reg = <6>; + }; + + port@7 { + reg = <7>; + }; + + port@8 { + reg = <8>; + }; + + port@9 { + reg = <9>; + }; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index d6c90161c7bf..6bd7df1c3e08 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14158,6 +14158,13 @@ M: Sean Wang <sean.wang@mediatek.com> S: Maintained F: drivers/char/hw_random/mtk-rng.c +MEDIATEK ISP3.0 DRIVER +M: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +M: Julien Stephan <jstephan@baylibre.com> +M: Andy Hsieh <andy.hsieh@mediatek.com> +S: Supported +F: Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml + MEDIATEK SMI DRIVER M: Yong Wu <yong.wu@mediatek.com> L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)