| Message ID | 20240707231331.3433340-3-sunyeal.hong@samsung.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [v2,1/4] dt-bindings: clock: add Exynos Auto v920 SoC CMU bindings | expand |
> -----Original Message----- > From: Sunyeal Hong <sunyeal.hong@samsung.com> > Sent: Monday, July 8, 2024 4:43 AM > To: Krzysztof Kozlowski <krzk@kernel.org>; Sylwester Nawrocki > <s.nawrocki@samsung.com>; Chanwoo Choi <cw00.choi@samsung.com>; > Alim Akhtar <alim.akhtar@samsung.com>; Michael Turquette > <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Rob > Herring <robh@kernel.org>; Conor Dooley <conor+dt@kernel.org> > Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org; Sunyeal Hong <sunyeal.hong@samsung.com> > Subject: [PATCH v2 2/4] arm64: dts: exynos: add initial CMU clock nodes in > Exynos Auto v920 > > Add cmu_top, cmu_peric0 clock nodes and > switch USI clocks instead of dummy fixed-rate-clock. > > Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> > --- > .../arm64/boot/dts/exynos/exynosautov920.dtsi | 40 +++++++++++++------ > 1 file changed, 27 insertions(+), 13 deletions(-) > > diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi > b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi > index c1c8566d74f5..54fc32074379 100644 > --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi > +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi > @@ -6,6 +6,7 @@ > * > */ > > +#include <dt-bindings/clock/samsung,exynosautov920.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/soc/samsung,exynos-usi.h> > > @@ -38,17 +39,6 @@ xtcxo: clock { > clock-output-names = "oscclk"; > }; > > - /* > - * FIXME: Keep the stub clock for serial driver, until proper clock > - * driver is implemented. > - */ > - clock_usi: clock-usi { > - compatible = "fixed-clock"; > - #clock-cells = <0>; > - clock-frequency = <200000000>; > - clock-output-names = "usi"; > - }; > - > cpus: cpus { > #address-cells = <2>; > #size-cells = <0>; > @@ -182,6 +172,28 @@ chipid@10000000 { > reg = <0x10000000 0x24>; > }; > > + cmu_peric0: clock-controller@10800000 { > + compatible = "samsung,exynosautov920-cmu- > peric0"; > + reg = <0x10800000 0x8000>; Please cross check the size of the register range, this looks to be more then what is needed. > + #clock-cells = <1>; > + > + clocks = <&xtcxo>, > + <&cmu_top DOUT_CLKCMU_PERIC0_NOC>, > + <&cmu_top DOUT_CLKCMU_PERIC0_IP>; > + clock-names = "oscclk", > + "noc", > + "ip"; > + }; > + > + cmu_top: clock-controller@11000000 { > + compatible = "samsung,exynosautov920-cmu-top"; > + reg = <0x11000000 0x8000>; > + #clock-cells = <1>; > + > + clocks = <&xtcxo>; > + clock-names = "oscclk"; > + }; > + > gic: interrupt-controller@10400000 { > compatible = "arm,gic-v3"; > #interrupt-cells = <3>; > @@ -213,7 +225,8 @@ usi_0: usi@108800c0 { > #address-cells = <1>; > #size-cells = <1>; > ranges; > - clocks = <&clock_usi>, <&clock_usi>; > + clocks = <&cmu_peric0 > CLK_MOUT_PERIC0_NOC_USER>, > + <&cmu_peric0 > CLK_DOUT_PERIC0_USI00_USI>; > clock-names = "pclk", "ipclk"; > status = "disabled"; > > @@ -224,7 +237,8 @@ serial_0: serial@10880000 { > interrupts = <GIC_SPI 764 > IRQ_TYPE_LEVEL_HIGH>; > pinctrl-names = "default"; > pinctrl-0 = <&uart0_bus>; > - clocks = <&clock_usi>, <&clock_usi>; > + clocks = <&cmu_peric0 > CLK_MOUT_PERIC0_NOC_USER>, > + <&cmu_peric0 > CLK_DOUT_PERIC0_USI00_USI>; > clock-names = "uart", "clk_uart_baud0"; > samsung,uart-fifosize = <256>; > status = "disabled"; > -- > 2.45.2
Hello Alim, > -----Original Message----- > From: Alim Akhtar <alim.akhtar@samsung.com> > Sent: Monday, July 8, 2024 8:05 PM > To: 'Sunyeal Hong' <sunyeal.hong@samsung.com>; 'Krzysztof Kozlowski' > <krzk@kernel.org>; 'Sylwester Nawrocki' <s.nawrocki@samsung.com>; 'Chanwoo > Choi' <cw00.choi@samsung.com>; 'Michael Turquette' > <mturquette@baylibre.com>; 'Stephen Boyd' <sboyd@kernel.org>; 'Rob > Herring' <robh@kernel.org>; 'Conor Dooley' <conor+dt@kernel.org> > Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org > Subject: RE: [PATCH v2 2/4] arm64: dts: exynos: add initial CMU clock > nodes in Exynos Auto v920 > > > > > -----Original Message----- > > From: Sunyeal Hong <sunyeal.hong@samsung.com> > > Sent: Monday, July 8, 2024 4:43 AM > > To: Krzysztof Kozlowski <krzk@kernel.org>; Sylwester Nawrocki > > <s.nawrocki@samsung.com>; Chanwoo Choi <cw00.choi@samsung.com>; Alim > > Akhtar <alim.akhtar@samsung.com>; Michael Turquette > > <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Rob > > Herring <robh@kernel.org>; Conor Dooley <conor+dt@kernel.org> > > Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; > > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > > linux- kernel@vger.kernel.org; Sunyeal Hong <sunyeal.hong@samsung.com> > > Subject: [PATCH v2 2/4] arm64: dts: exynos: add initial CMU clock > > nodes in Exynos Auto v920 > > > > Add cmu_top, cmu_peric0 clock nodes and switch USI clocks instead of > > dummy fixed-rate-clock. > > > > Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> > > --- > > .../arm64/boot/dts/exynos/exynosautov920.dtsi | 40 > > +++++++++++++------ > > 1 file changed, 27 insertions(+), 13 deletions(-) > > > > diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi > > b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi > > index c1c8566d74f5..54fc32074379 100644 > > --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi > > +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi > > @@ -6,6 +6,7 @@ > > * > > */ > > > > +#include <dt-bindings/clock/samsung,exynosautov920.h> > > #include <dt-bindings/interrupt-controller/arm-gic.h> > > #include <dt-bindings/soc/samsung,exynos-usi.h> > > > > @@ -38,17 +39,6 @@ xtcxo: clock { > > clock-output-names = "oscclk"; > > }; > > > > - /* > > - * FIXME: Keep the stub clock for serial driver, until proper clock > > - * driver is implemented. > > - */ > > - clock_usi: clock-usi { > > - compatible = "fixed-clock"; > > - #clock-cells = <0>; > > - clock-frequency = <200000000>; > > - clock-output-names = "usi"; > > - }; > > - > > cpus: cpus { > > #address-cells = <2>; > > #size-cells = <0>; > > @@ -182,6 +172,28 @@ chipid@10000000 { > > reg = <0x10000000 0x24>; > > }; > > > > + cmu_peric0: clock-controller@10800000 { > > + compatible = "samsung,exynosautov920-cmu- > > peric0"; > > + reg = <0x10800000 0x8000>; > Please cross check the size of the register range, this looks to be more > then what is needed. > In the case of preic0, the size is up to 0x7088. The CMU block SFR area of ExynosAuto v920 is generally specified up to 0x8000. There are differences for each block, but the settings are the same. Do you think it is necessary to change the actual size of each block? > > + #clock-cells = <1>; > > + > > + clocks = <&xtcxo>, > > + <&cmu_top DOUT_CLKCMU_PERIC0_NOC>, > > + <&cmu_top DOUT_CLKCMU_PERIC0_IP>; > > + clock-names = "oscclk", > > + "noc", > > + "ip"; > > + }; > > + > > + cmu_top: clock-controller@11000000 { > > + compatible = "samsung,exynosautov920-cmu-top"; > > + reg = <0x11000000 0x8000>; > > + #clock-cells = <1>; > > + > > + clocks = <&xtcxo>; > > + clock-names = "oscclk"; > > + }; > > + > > gic: interrupt-controller@10400000 { > > compatible = "arm,gic-v3"; > > #interrupt-cells = <3>; > > @@ -213,7 +225,8 @@ usi_0: usi@108800c0 { > > #address-cells = <1>; > > #size-cells = <1>; > > ranges; > > - clocks = <&clock_usi>, <&clock_usi>; > > + clocks = <&cmu_peric0 > > CLK_MOUT_PERIC0_NOC_USER>, > > + <&cmu_peric0 > > CLK_DOUT_PERIC0_USI00_USI>; > > clock-names = "pclk", "ipclk"; > > status = "disabled"; > > > > @@ -224,7 +237,8 @@ serial_0: serial@10880000 { > > interrupts = <GIC_SPI 764 > > IRQ_TYPE_LEVEL_HIGH>; > > pinctrl-names = "default"; > > pinctrl-0 = <&uart0_bus>; > > - clocks = <&clock_usi>, <&clock_usi>; > > + clocks = <&cmu_peric0 > > CLK_MOUT_PERIC0_NOC_USER>, > > + <&cmu_peric0 > > CLK_DOUT_PERIC0_USI00_USI>; > > clock-names = "uart", "clk_uart_baud0"; > > samsung,uart-fifosize = <256>; > > status = "disabled"; > > -- > > 2.45.2 > > Please review my answer again. Thanks, Sunyeal Hong
Hello Sunyeal, > -----Original Message----- > From: sunyeal.hong <sunyeal.hong@samsung.com> > [snip] > > Subject: RE: [PATCH v2 2/4] arm64: dts: exynos: add initial CMU clock > > nodes in Exynos Auto v920 > > > > > > > > > -----Original Message----- > > > From: Sunyeal Hong <sunyeal.hong@samsung.com> > > > Sent: Monday, July 8, 2024 4:43 AM > > > To: Krzysztof Kozlowski <krzk@kernel.org>; Sylwester Nawrocki > > > <s.nawrocki@samsung.com>; Chanwoo Choi > <cw00.choi@samsung.com>; Alim > > > Akhtar <alim.akhtar@samsung.com>; Michael Turquette [Snip] > > > + cmu_peric0: clock-controller@10800000 { > > > + compatible = "samsung,exynosautov920-cmu- > > > peric0"; > > > + reg = <0x10800000 0x8000>; > > Please cross check the size of the register range, this looks to be > > more then what is needed. > > > In the case of preic0, the size is up to 0x7088. The CMU block SFR area of > ExynosAuto v920 is generally specified up to 0x8000. There are differences > for each block, but the settings are the same. > Do you think it is necessary to change the actual size of each block? To avoid any overlap between difference SFR region, better to mention the exact size of the SFR region. [snip] > > > -- > > > 2.45.2 > > > > > > Please review my answer again. > > Thanks, > Sunyeal Hong >
Hello Alim, > -----Original Message----- > From: Alim Akhtar <alim.akhtar@samsung.com> > Sent: Wednesday, July 10, 2024 11:31 AM > To: 'sunyeal.hong' <sunyeal.hong@samsung.com>; 'Krzysztof Kozlowski' > <krzk@kernel.org>; 'Sylwester Nawrocki' <s.nawrocki@samsung.com>; 'Chanwoo > Choi' <cw00.choi@samsung.com>; 'Michael Turquette' > <mturquette@baylibre.com>; 'Stephen Boyd' <sboyd@kernel.org>; 'Rob > Herring' <robh@kernel.org>; 'Conor Dooley' <conor+dt@kernel.org> > Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org > Subject: RE: [PATCH v2 2/4] arm64: dts: exynos: add initial CMU clock > nodes in Exynos Auto v920 > > Hello Sunyeal, > > > -----Original Message----- > > From: sunyeal.hong <sunyeal.hong@samsung.com> > > > [snip] > > > Subject: RE: [PATCH v2 2/4] arm64: dts: exynos: add initial CMU > > > clock nodes in Exynos Auto v920 > > > > > > > > > > > > > -----Original Message----- > > > > From: Sunyeal Hong <sunyeal.hong@samsung.com> > > > > Sent: Monday, July 8, 2024 4:43 AM > > > > To: Krzysztof Kozlowski <krzk@kernel.org>; Sylwester Nawrocki > > > > <s.nawrocki@samsung.com>; Chanwoo Choi > > <cw00.choi@samsung.com>; Alim > > > > Akhtar <alim.akhtar@samsung.com>; Michael Turquette > [Snip] > > > > + cmu_peric0: clock-controller@10800000 { > > > > + compatible = "samsung,exynosautov920-cmu- > > > > peric0"; > > > > + reg = <0x10800000 0x8000>; > > > Please cross check the size of the register range, this looks to be > > > more then what is needed. > > > > > In the case of preic0, the size is up to 0x7088. The CMU block SFR > > area of ExynosAuto v920 is generally specified up to 0x8000. There > > are differences for each block, but the settings are the same. > > Do you think it is necessary to change the actual size of each block? > To avoid any overlap between difference SFR region, better to mention the > exact size of the SFR region. > In ExynosAuto, the SFR of each block has an offset of 0x10000. So I don't think SFR will be overlapped. In the case of CMU SFR, there is no size over 0x8000, so I think it would be better to maintain that value. Please give me your opinion again. > [snip] > > > > -- > > > > 2.45.2 > > > > > > > > > > Please review my answer again. > > > > Thanks, > > Sunyeal Hong > > > > Thanks, Sunyeal Hong
> -----Original Message----- > From: sunyeal.hong <sunyeal.hong@samsung.com> > Sent: Wednesday, July 10, 2024 12:29 PM > To: 'Alim Akhtar' <alim.akhtar@samsung.com>; 'Krzysztof Kozlowski' > <krzk@kernel.org>; 'Sylwester Nawrocki' <s.nawrocki@samsung.com>; > 'Chanwoo Choi' <cw00.choi@samsung.com>; 'Michael Turquette' > <mturquette@baylibre.com>; 'Stephen Boyd' <sboyd@kernel.org>; 'Rob > Herring' <robh@kernel.org>; 'Conor Dooley' <conor+dt@kernel.org> > Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org > Subject: RE: [PATCH v2 2/4] arm64: dts: exynos: add initial CMU clock nodes > in Exynos Auto v920 > > Hello Alim, > > > -----Original Message----- > > From: Alim Akhtar <alim.akhtar@samsung.com> > > Sent: Wednesday, July 10, 2024 11:31 AM > > To: 'sunyeal.hong' <sunyeal.hong@samsung.com>; 'Krzysztof Kozlowski' > > <krzk@kernel.org>; 'Sylwester Nawrocki' <s.nawrocki@samsung.com>; > > 'Chanwoo Choi' <cw00.choi@samsung.com>; 'Michael Turquette' > > <mturquette@baylibre.com>; 'Stephen Boyd' <sboyd@kernel.org>; 'Rob > > Herring' <robh@kernel.org>; 'Conor Dooley' <conor+dt@kernel.org> > > Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; > > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > > linux- kernel@vger.kernel.org > > Subject: RE: [PATCH v2 2/4] arm64: dts: exynos: add initial CMU clock > > nodes in Exynos Auto v920 > > > > Hello Sunyeal, > > > > > -----Original Message----- > > > From: sunyeal.hong <sunyeal.hong@samsung.com> > > > > > [snip] > > > > Subject: RE: [PATCH v2 2/4] arm64: dts: exynos: add initial CMU > > > > clock nodes in Exynos Auto v920 > > > > > > > > > > > > > > > > > -----Original Message----- > > > > > From: Sunyeal Hong <sunyeal.hong@samsung.com> > > > > > Sent: Monday, July 8, 2024 4:43 AM > > > > > To: Krzysztof Kozlowski <krzk@kernel.org>; Sylwester Nawrocki > > > > > <s.nawrocki@samsung.com>; Chanwoo Choi > > > <cw00.choi@samsung.com>; Alim > > > > > Akhtar <alim.akhtar@samsung.com>; Michael Turquette > > [Snip] > > > > > + cmu_peric0: clock-controller@10800000 { > > > > > + compatible = "samsung,exynosautov920- > cmu- > > > > > peric0"; > > > > > + reg = <0x10800000 0x8000>; > > > > Please cross check the size of the register range, this looks to > > > > be more then what is needed. > > > > > > > In the case of preic0, the size is up to 0x7088. The CMU block SFR > > > area of ExynosAuto v920 is generally specified up to 0x8000. There > > > are differences for each block, but the settings are the same. > > > Do you think it is necessary to change the actual size of each block? > > To avoid any overlap between difference SFR region, better to mention > > the exact size of the SFR region. > > > In ExynosAuto, the SFR of each block has an offset of 0x10000. So I don't > think SFR will be overlapped. > In the case of CMU SFR, there is no size over 0x8000, so I think it would be > better to maintain that value. > Please give me your opinion again. Ok, you keep size as 0x8000 > > [snip] > > > > > -- > > > > > 2.45.2 > > > > > > > > > > > > > > Please review my answer again. > > > > > > Thanks, > > > Sunyeal Hong > > > > > > > > > Thanks, > Sunyeal Hong >
diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi index c1c8566d74f5..54fc32074379 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -6,6 +6,7 @@ * */ +#include <dt-bindings/clock/samsung,exynosautov920.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/soc/samsung,exynos-usi.h> @@ -38,17 +39,6 @@ xtcxo: clock { clock-output-names = "oscclk"; }; - /* - * FIXME: Keep the stub clock for serial driver, until proper clock - * driver is implemented. - */ - clock_usi: clock-usi { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - clock-output-names = "usi"; - }; - cpus: cpus { #address-cells = <2>; #size-cells = <0>; @@ -182,6 +172,28 @@ chipid@10000000 { reg = <0x10000000 0x24>; }; + cmu_peric0: clock-controller@10800000 { + compatible = "samsung,exynosautov920-cmu-peric0"; + reg = <0x10800000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_PERIC0_NOC>, + <&cmu_top DOUT_CLKCMU_PERIC0_IP>; + clock-names = "oscclk", + "noc", + "ip"; + }; + + cmu_top: clock-controller@11000000 { + compatible = "samsung,exynosautov920-cmu-top"; + reg = <0x11000000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>; + clock-names = "oscclk"; + }; + gic: interrupt-controller@10400000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; @@ -213,7 +225,8 @@ usi_0: usi@108800c0 { #address-cells = <1>; #size-cells = <1>; ranges; - clocks = <&clock_usi>, <&clock_usi>; + clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>; clock-names = "pclk", "ipclk"; status = "disabled"; @@ -224,7 +237,8 @@ serial_0: serial@10880000 { interrupts = <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&uart0_bus>; - clocks = <&clock_usi>, <&clock_usi>; + clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <256>; status = "disabled";
Add cmu_top, cmu_peric0 clock nodes and switch USI clocks instead of dummy fixed-rate-clock. Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> --- .../arm64/boot/dts/exynos/exynosautov920.dtsi | 40 +++++++++++++------ 1 file changed, 27 insertions(+), 13 deletions(-)