| Message ID | 20240708222304.2728412-1-hauke@hauke-m.de (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 9c7a86c935074525f24cc20e78a7d5150e4600e3 |
| Headers | show |
| Series | MIPS: lantiq: improve USB initialization | expand |
On Tue, Jul 09, 2024 at 12:23:04AM +0200, Hauke Mehrtens wrote: > This adds code to initialize the USB controller and PHY also on Danube, > Amazon SE and AR10. This code is based on the Vendor driver from > different UGW versions and compared to the hardware documentation. > > This patch is included in OpenWrt for many years. > > Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> > --- > arch/mips/lantiq/xway/sysctrl.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c > index 3ed078225222..5a75283d17f1 100644 > --- a/arch/mips/lantiq/xway/sysctrl.c > +++ b/arch/mips/lantiq/xway/sysctrl.c > @@ -247,6 +247,25 @@ static void pmu_disable(struct clk *clk) > pr_warn("deactivating PMU module failed!"); > } > > +static void usb_set_clock(void) > +{ > + unsigned int val = ltq_cgu_r32(ifccr); > + > + if (of_machine_is_compatible("lantiq,ar10") || > + of_machine_is_compatible("lantiq,grx390")) { > + val &= ~0x03; /* XTAL divided by 3 */ > + } else if (of_machine_is_compatible("lantiq,ar9") || > + of_machine_is_compatible("lantiq,vr9")) { > + /* TODO: this depends on the XTAL frequency */ > + val |= 0x03; /* XTAL divided by 3 */ > + } else if (of_machine_is_compatible("lantiq,ase")) { > + val |= 0x20; /* from XTAL */ > + } else if (of_machine_is_compatible("lantiq,danube")) { > + val |= 0x30; /* 12 MHz, generated from 36 MHz */ > + } > + ltq_cgu_w32(val, ifccr); > +} > + > /* the pci enable helper */ > static int pci_enable(struct clk *clk) > { > @@ -588,4 +607,5 @@ void __init ltq_soc_init(void) > clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE); > clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0); > } > + usb_set_clock(); > } > -- > 2.45.2 applied to mips-next. Thomas.
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c index 3ed078225222..5a75283d17f1 100644 --- a/arch/mips/lantiq/xway/sysctrl.c +++ b/arch/mips/lantiq/xway/sysctrl.c @@ -247,6 +247,25 @@ static void pmu_disable(struct clk *clk) pr_warn("deactivating PMU module failed!"); } +static void usb_set_clock(void) +{ + unsigned int val = ltq_cgu_r32(ifccr); + + if (of_machine_is_compatible("lantiq,ar10") || + of_machine_is_compatible("lantiq,grx390")) { + val &= ~0x03; /* XTAL divided by 3 */ + } else if (of_machine_is_compatible("lantiq,ar9") || + of_machine_is_compatible("lantiq,vr9")) { + /* TODO: this depends on the XTAL frequency */ + val |= 0x03; /* XTAL divided by 3 */ + } else if (of_machine_is_compatible("lantiq,ase")) { + val |= 0x20; /* from XTAL */ + } else if (of_machine_is_compatible("lantiq,danube")) { + val |= 0x30; /* 12 MHz, generated from 36 MHz */ + } + ltq_cgu_w32(val, ifccr); +} + /* the pci enable helper */ static int pci_enable(struct clk *clk) { @@ -588,4 +607,5 @@ void __init ltq_soc_init(void) clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE); clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0); } + usb_set_clock(); }
This adds code to initialize the USB controller and PHY also on Danube, Amazon SE and AR10. This code is based on the Vendor driver from different UGW versions and compared to the hardware documentation. This patch is included in OpenWrt for many years. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> --- arch/mips/lantiq/xway/sysctrl.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)