| Message ID | 20240711-smcntrpmf_v7-v8-13-b7c38ae7b263@rivosinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add RISC-V ISA extension smcntrpmf support | expand |
On Fri, Jul 12, 2024 at 8:34 AM Atish Patra <atishp@rivosinc.com> wrote: > > Create a new config for Smcntrpmf extension so that it can be enabled/ > disabled from the qemu commandline. > > Signed-off-by: Atish Patra <atishp@rivosinc.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 63f553c92b00..ef50130a91e7 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1468,6 +1468,7 @@ const char *riscv_get_misa_ext_description(uint32_t bit) > const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { > /* Defaults for standard extensions */ > MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), > + MULTI_EXT_CFG_BOOL("smcntrpmf", ext_smcntrpmf, false), > MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true), > MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true), > MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true), > > -- > 2.34.1 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 63f553c92b00..ef50130a91e7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1468,6 +1468,7 @@ const char *riscv_get_misa_ext_description(uint32_t bit) const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { /* Defaults for standard extensions */ MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), + MULTI_EXT_CFG_BOOL("smcntrpmf", ext_smcntrpmf, false), MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true), MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true), MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true),
Create a new config for Smcntrpmf extension so that it can be enabled/ disabled from the qemu commandline. Signed-off-by: Atish Patra <atishp@rivosinc.com> --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+)