| Message ID | 20240718081636.879544-5-zhenzhong.duan@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | intel_iommu: Enable stage-1 translation for emulated device | expand |
On 18/07/2024 10:16, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe. > > > Per spec 6.5.2.4, PADID-selective PASID-based iotlb invalidation will > flush stage-2 iotlb entries with matching domain id and pasid. > > With scalable modern mode introduced, guest could send PASID-selective > PASID-based iotlb invalidation to flush both stage-1 and stage-2 entries. > > Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> > --- > hw/i386/intel_iommu_internal.h | 10 +++++ > hw/i386/intel_iommu.c | 78 ++++++++++++++++++++++++++++++++++ > 2 files changed, 88 insertions(+) > > diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h > index 4e0331caba..f71fc91234 100644 > --- a/hw/i386/intel_iommu_internal.h > +++ b/hw/i386/intel_iommu_internal.h > @@ -440,6 +440,16 @@ typedef union VTDInvDesc VTDInvDesc; > (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \ > (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) > > +#define VTD_INV_DESC_PIOTLB_ALL_IN_PASID (2ULL << 4) > +#define VTD_INV_DESC_PIOTLB_PSI_IN_PASID (3ULL << 4) > + > +#define VTD_INV_DESC_PIOTLB_RSVD_VAL0 0xfff000000000ffc0ULL > +#define VTD_INV_DESC_PIOTLB_RSVD_VAL1 0xf80ULL > + > +#define VTD_INV_DESC_PIOTLB_PASID(val) (((val) >> 32) & 0xfffffULL) > +#define VTD_INV_DESC_PIOTLB_DID(val) (((val) >> 16) & \ > + VTD_DOMAIN_ID_MASK) > + > /* Information about page-selective IOTLB invalidate */ > struct VTDIOTLBPageInvInfo { > uint16_t domain_id; > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c > index 40cbd4a0f4..075a27adac 100644 > --- a/hw/i386/intel_iommu.c > +++ b/hw/i386/intel_iommu.c > @@ -2659,6 +2659,80 @@ static bool vtd_process_iotlb_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) > return true; > } > > +static gboolean vtd_hash_remove_by_pasid(gpointer key, gpointer value, > + gpointer user_data) > +{ > + VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value; > + VTDIOTLBPageInvInfo *info = (VTDIOTLBPageInvInfo *)user_data; > + > + return ((entry->domain_id == info->domain_id) && > + (entry->pasid == info->pasid)); > +} > + > +static void vtd_piotlb_pasid_invalidate(IntelIOMMUState *s, > + uint16_t domain_id, uint32_t pasid) > +{ > + VTDIOTLBPageInvInfo info; > + VTDAddressSpace *vtd_as; > + VTDContextEntry ce; > + > + info.domain_id = domain_id; > + info.pasid = pasid; > + > + vtd_iommu_lock(s); > + g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_pasid, > + &info); > + vtd_iommu_unlock(s); > + > + QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) { > + if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), > + vtd_as->devfn, &ce) && > + domain_id == vtd_get_domain_id(s, &ce, vtd_as->pasid)) { > + uint32_t rid2pasid = VTD_CE_GET_RID2PASID(&ce); > + > + if ((vtd_as->pasid != PCI_NO_PASID || pasid != rid2pasid) && > + vtd_as->pasid != pasid) { > + continue; > + } > + > + if (!s->scalable_modern) { > + vtd_address_space_sync(vtd_as); > + } > + } > + } > +} > + > +static bool vtd_process_piotlb_desc(IntelIOMMUState *s, > + VTDInvDesc *inv_desc) > +{ > + uint16_t domain_id; > + uint32_t pasid; > + > + if ((inv_desc->val[0] & VTD_INV_DESC_PIOTLB_RSVD_VAL0) || > + (inv_desc->val[1] & VTD_INV_DESC_PIOTLB_RSVD_VAL1)) { > + error_report_once("non-zero-field-in-piotlb_inv_desc hi: 0x%" PRIx64 > + " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]); This error is not formatted as the other similar messages we print when reserved bits are non-zero. Here is what we've done in vtd_process_iotlb_desc: error_report_once("%s: invalid iotlb inv desc: hi=0x%"PRIx64 ", lo=0x%"PRIx64" (reserved bits unzero)", __func__, inv_desc->hi, inv_desc->lo); > + return false; > + } > + > + domain_id = VTD_INV_DESC_PIOTLB_DID(inv_desc->val[0]); > + pasid = VTD_INV_DESC_PIOTLB_PASID(inv_desc->val[0]); > + switch (inv_desc->val[0] & VTD_INV_DESC_IOTLB_G) { Not critical but why don't we have VTD_INV_DESC_PIOTLB_G? > + case VTD_INV_DESC_PIOTLB_ALL_IN_PASID: > + vtd_piotlb_pasid_invalidate(s, domain_id, pasid); > + break; > + > + case VTD_INV_DESC_PIOTLB_PSI_IN_PASID: > + break; > + > + default: > + error_report_once("Invalid granularity in P-IOTLB desc hi: 0x%" PRIx64 > + " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]); Same comment, I think we should make the messages consistent across descriptor handlers. > + return false; > + } > + return true; > +} > + > static bool vtd_process_inv_iec_desc(IntelIOMMUState *s, > VTDInvDesc *inv_desc) > { > @@ -2769,6 +2843,10 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s) > break; > > case VTD_INV_DESC_PIOTLB: > + trace_vtd_inv_desc("p-iotlb", inv_desc.val[1], inv_desc.val[0]); > + if (!vtd_process_piotlb_desc(s, &inv_desc)) { > + return false; > + } > break; > > case VTD_INV_DESC_WAIT: > -- > 2.34.1 >
>-----Original Message----- >From: CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com> >Subject: Re: [PATCH v1 04/17] intel_iommu: Flush stage-2 cache in PADID- >selective PASID-based iotlb invalidation > > > >On 18/07/2024 10:16, Zhenzhong Duan wrote: >> Caution: External email. Do not open attachments or click links, unless this >email comes from a known sender and you know the content is safe. >> >> >> Per spec 6.5.2.4, PADID-selective PASID-based iotlb invalidation will >> flush stage-2 iotlb entries with matching domain id and pasid. >> >> With scalable modern mode introduced, guest could send PASID-selective >> PASID-based iotlb invalidation to flush both stage-1 and stage-2 entries. >> >> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> >> --- >> hw/i386/intel_iommu_internal.h | 10 +++++ >> hw/i386/intel_iommu.c | 78 >++++++++++++++++++++++++++++++++++ >> 2 files changed, 88 insertions(+) >> >> diff --git a/hw/i386/intel_iommu_internal.h >b/hw/i386/intel_iommu_internal.h >> index 4e0331caba..f71fc91234 100644 >> --- a/hw/i386/intel_iommu_internal.h >> +++ b/hw/i386/intel_iommu_internal.h >> @@ -440,6 +440,16 @@ typedef union VTDInvDesc VTDInvDesc; >> (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | >VTD_SL_TM)) : \ >> (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) >> >> +#define VTD_INV_DESC_PIOTLB_ALL_IN_PASID (2ULL << 4) >> +#define VTD_INV_DESC_PIOTLB_PSI_IN_PASID (3ULL << 4) >> + >> +#define VTD_INV_DESC_PIOTLB_RSVD_VAL0 0xfff000000000ffc0ULL >> +#define VTD_INV_DESC_PIOTLB_RSVD_VAL1 0xf80ULL >> + >> +#define VTD_INV_DESC_PIOTLB_PASID(val) (((val) >> 32) & 0xfffffULL) >> +#define VTD_INV_DESC_PIOTLB_DID(val) (((val) >> 16) & \ >> + VTD_DOMAIN_ID_MASK) >> + >> /* Information about page-selective IOTLB invalidate */ >> struct VTDIOTLBPageInvInfo { >> uint16_t domain_id; >> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c >> index 40cbd4a0f4..075a27adac 100644 >> --- a/hw/i386/intel_iommu.c >> +++ b/hw/i386/intel_iommu.c >> @@ -2659,6 +2659,80 @@ static bool >vtd_process_iotlb_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) >> return true; >> } >> >> +static gboolean vtd_hash_remove_by_pasid(gpointer key, gpointer value, >> + gpointer user_data) >> +{ >> + VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value; >> + VTDIOTLBPageInvInfo *info = (VTDIOTLBPageInvInfo *)user_data; >> + >> + return ((entry->domain_id == info->domain_id) && >> + (entry->pasid == info->pasid)); >> +} >> + >> +static void vtd_piotlb_pasid_invalidate(IntelIOMMUState *s, >> + uint16_t domain_id, uint32_t pasid) >> +{ >> + VTDIOTLBPageInvInfo info; >> + VTDAddressSpace *vtd_as; >> + VTDContextEntry ce; >> + >> + info.domain_id = domain_id; >> + info.pasid = pasid; >> + >> + vtd_iommu_lock(s); >> + g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_pasid, >> + &info); >> + vtd_iommu_unlock(s); >> + >> + QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) { >> + if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), >> + vtd_as->devfn, &ce) && >> + domain_id == vtd_get_domain_id(s, &ce, vtd_as->pasid)) { >> + uint32_t rid2pasid = VTD_CE_GET_RID2PASID(&ce); >> + >> + if ((vtd_as->pasid != PCI_NO_PASID || pasid != rid2pasid) && >> + vtd_as->pasid != pasid) { >> + continue; >> + } >> + >> + if (!s->scalable_modern) { >> + vtd_address_space_sync(vtd_as); >> + } >> + } >> + } >> +} >> + >> +static bool vtd_process_piotlb_desc(IntelIOMMUState *s, >> + VTDInvDesc *inv_desc) >> +{ >> + uint16_t domain_id; >> + uint32_t pasid; >> + >> + if ((inv_desc->val[0] & VTD_INV_DESC_PIOTLB_RSVD_VAL0) || >> + (inv_desc->val[1] & VTD_INV_DESC_PIOTLB_RSVD_VAL1)) { >> + error_report_once("non-zero-field-in-piotlb_inv_desc hi: 0x%" >PRIx64 >> + " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]); >This error is not formatted as the other similar messages we print when >reserved bits are non-zero. >Here is what we've done in vtd_process_iotlb_desc: Sure, will change as below, > > error_report_once("%s: invalid iotlb inv desc: hi=0x%"PRIx64 > ", lo=0x%"PRIx64" (reserved bits unzero)", > __func__, inv_desc->hi, inv_desc->lo); >> + return false; >> + } >> + >> + domain_id = VTD_INV_DESC_PIOTLB_DID(inv_desc->val[0]); >> + pasid = VTD_INV_DESC_PIOTLB_PASID(inv_desc->val[0]); >> + switch (inv_desc->val[0] & VTD_INV_DESC_IOTLB_G) { >Not critical but why don't we have VTD_INV_DESC_PIOTLB_G? Will add. >> + case VTD_INV_DESC_PIOTLB_ALL_IN_PASID: >> + vtd_piotlb_pasid_invalidate(s, domain_id, pasid); >> + break; >> + >> + case VTD_INV_DESC_PIOTLB_PSI_IN_PASID: >> + break; >> + >> + default: >> + error_report_once("Invalid granularity in P-IOTLB desc hi: 0x%" >PRIx64 >> + " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]); >Same comment, I think we should make the messages consistent across >descriptor handlers. What about below: diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 3290761595..e76fd9d377 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -479,9 +479,10 @@ typedef union VTDInvDesc VTDInvDesc; #define VTD_INV_DESC_PIOTLB_ALL_IN_PASID (2ULL << 4) #define VTD_INV_DESC_PIOTLB_PSI_IN_PASID (3ULL << 4) +/* Masks for IOTLB Invalidate Descriptor */ +#define VTD_INV_DESC_IOTLB_G (3ULL << 4) #define VTD_INV_DESC_PIOTLB_RSVD_VAL0 0xfff000000000ffc0ULL #define VTD_INV_DESC_PIOTLB_RSVD_VAL1 0xf80ULL - #define VTD_INV_DESC_PIOTLB_PASID(val) (((val) >> 32) & 0xfffffULL) #define VTD_INV_DESC_PIOTLB_DID(val) (((val) >> 16) & \ VTD_DOMAIN_ID_MASK) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 0733180501..9dd41b835b 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3708,8 +3708,9 @@ static bool vtd_process_piotlb_desc(IntelIOMMUState *s, if ((inv_desc->val[0] & VTD_INV_DESC_PIOTLB_RSVD_VAL0) || (inv_desc->val[1] & VTD_INV_DESC_PIOTLB_RSVD_VAL1)) { - error_report_once("non-zero-field-in-piotlb_inv_desc hi: 0x%" PRIx64 - " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]); + error_report_once("%s: invalid piotlb inv desc hi=0x%"PRIx64 + " lo=0x%"PRIx64" (reserved bits unzero)", + __func__, inv_desc->val[1], inv_desc->val[0]); return false; } @@ -3728,8 +3729,10 @@ static bool vtd_process_piotlb_desc(IntelIOMMUState *s, break; default: - error_report_once("Invalid granularity in P-IOTLB desc hi: 0x%" PRIx64 - " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]); + error_report_once("%s: invalid piotlb inv desc: hi=0x%"PRIx64 + ", lo=0x%"PRIx64" (type mismatch: 0x%llx)", + __func__, inv_desc->val[1], inv_desc->val[0], + inv_desc->val[0] & VTD_INV_DESC_IOTLB_G); return false; } return true; Thanks Zhenzhong
On 24/07/2024 04:59, Duan, Zhenzhong wrote: > Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe. > > >> -----Original Message----- >> From: CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com> >> Subject: Re: [PATCH v1 04/17] intel_iommu: Flush stage-2 cache in PADID- >> selective PASID-based iotlb invalidation >> >> >> >> On 18/07/2024 10:16, Zhenzhong Duan wrote: >>> Caution: External email. Do not open attachments or click links, unless this >> email comes from a known sender and you know the content is safe. >>> >>> Per spec 6.5.2.4, PADID-selective PASID-based iotlb invalidation will >>> flush stage-2 iotlb entries with matching domain id and pasid. >>> >>> With scalable modern mode introduced, guest could send PASID-selective >>> PASID-based iotlb invalidation to flush both stage-1 and stage-2 entries. >>> >>> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> >>> --- >>> hw/i386/intel_iommu_internal.h | 10 +++++ >>> hw/i386/intel_iommu.c | 78 >> ++++++++++++++++++++++++++++++++++ >>> 2 files changed, 88 insertions(+) >>> >>> diff --git a/hw/i386/intel_iommu_internal.h >> b/hw/i386/intel_iommu_internal.h >>> index 4e0331caba..f71fc91234 100644 >>> --- a/hw/i386/intel_iommu_internal.h >>> +++ b/hw/i386/intel_iommu_internal.h >>> @@ -440,6 +440,16 @@ typedef union VTDInvDesc VTDInvDesc; >>> (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | >> VTD_SL_TM)) : \ >>> (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) >>> >>> +#define VTD_INV_DESC_PIOTLB_ALL_IN_PASID (2ULL << 4) >>> +#define VTD_INV_DESC_PIOTLB_PSI_IN_PASID (3ULL << 4) >>> + >>> +#define VTD_INV_DESC_PIOTLB_RSVD_VAL0 0xfff000000000ffc0ULL >>> +#define VTD_INV_DESC_PIOTLB_RSVD_VAL1 0xf80ULL >>> + >>> +#define VTD_INV_DESC_PIOTLB_PASID(val) (((val) >> 32) & 0xfffffULL) >>> +#define VTD_INV_DESC_PIOTLB_DID(val) (((val) >> 16) & \ >>> + VTD_DOMAIN_ID_MASK) >>> + >>> /* Information about page-selective IOTLB invalidate */ >>> struct VTDIOTLBPageInvInfo { >>> uint16_t domain_id; >>> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c >>> index 40cbd4a0f4..075a27adac 100644 >>> --- a/hw/i386/intel_iommu.c >>> +++ b/hw/i386/intel_iommu.c >>> @@ -2659,6 +2659,80 @@ static bool >> vtd_process_iotlb_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) >>> return true; >>> } >>> >>> +static gboolean vtd_hash_remove_by_pasid(gpointer key, gpointer value, >>> + gpointer user_data) >>> +{ >>> + VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value; >>> + VTDIOTLBPageInvInfo *info = (VTDIOTLBPageInvInfo *)user_data; >>> + >>> + return ((entry->domain_id == info->domain_id) && >>> + (entry->pasid == info->pasid)); >>> +} >>> + >>> +static void vtd_piotlb_pasid_invalidate(IntelIOMMUState *s, >>> + uint16_t domain_id, uint32_t pasid) >>> +{ >>> + VTDIOTLBPageInvInfo info; >>> + VTDAddressSpace *vtd_as; >>> + VTDContextEntry ce; >>> + >>> + info.domain_id = domain_id; >>> + info.pasid = pasid; >>> + >>> + vtd_iommu_lock(s); >>> + g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_pasid, >>> + &info); >>> + vtd_iommu_unlock(s); >>> + >>> + QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) { >>> + if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), >>> + vtd_as->devfn, &ce) && >>> + domain_id == vtd_get_domain_id(s, &ce, vtd_as->pasid)) { >>> + uint32_t rid2pasid = VTD_CE_GET_RID2PASID(&ce); >>> + >>> + if ((vtd_as->pasid != PCI_NO_PASID || pasid != rid2pasid) && >>> + vtd_as->pasid != pasid) { >>> + continue; >>> + } >>> + >>> + if (!s->scalable_modern) { >>> + vtd_address_space_sync(vtd_as); >>> + } >>> + } >>> + } >>> +} >>> + >>> +static bool vtd_process_piotlb_desc(IntelIOMMUState *s, >>> + VTDInvDesc *inv_desc) >>> +{ >>> + uint16_t domain_id; >>> + uint32_t pasid; >>> + >>> + if ((inv_desc->val[0] & VTD_INV_DESC_PIOTLB_RSVD_VAL0) || >>> + (inv_desc->val[1] & VTD_INV_DESC_PIOTLB_RSVD_VAL1)) { >>> + error_report_once("non-zero-field-in-piotlb_inv_desc hi: 0x%" >> PRIx64 >>> + " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]); >> This error is not formatted as the other similar messages we print when >> reserved bits are non-zero. >> Here is what we've done in vtd_process_iotlb_desc: > Sure, will change as below, > >> error_report_once("%s: invalid iotlb inv desc: hi=0x%"PRIx64 >> ", lo=0x%"PRIx64" (reserved bits unzero)", >> __func__, inv_desc->hi, inv_desc->lo); >>> + return false; >>> + } >>> + >>> + domain_id = VTD_INV_DESC_PIOTLB_DID(inv_desc->val[0]); >>> + pasid = VTD_INV_DESC_PIOTLB_PASID(inv_desc->val[0]); >>> + switch (inv_desc->val[0] & VTD_INV_DESC_IOTLB_G) { >> Not critical but why don't we have VTD_INV_DESC_PIOTLB_G? > Will add. > >>> + case VTD_INV_DESC_PIOTLB_ALL_IN_PASID: >>> + vtd_piotlb_pasid_invalidate(s, domain_id, pasid); >>> + break; >>> + >>> + case VTD_INV_DESC_PIOTLB_PSI_IN_PASID: >>> + break; >>> + >>> + default: >>> + error_report_once("Invalid granularity in P-IOTLB desc hi: 0x%" >> PRIx64 >>> + " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]); >> Same comment, I think we should make the messages consistent across >> descriptor handlers. > What about below: > > diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h > index 3290761595..e76fd9d377 100644 > --- a/hw/i386/intel_iommu_internal.h > +++ b/hw/i386/intel_iommu_internal.h > @@ -479,9 +479,10 @@ typedef union VTDInvDesc VTDInvDesc; > #define VTD_INV_DESC_PIOTLB_ALL_IN_PASID (2ULL << 4) > #define VTD_INV_DESC_PIOTLB_PSI_IN_PASID (3ULL << 4) > > +/* Masks for IOTLB Invalidate Descriptor */ > +#define VTD_INV_DESC_IOTLB_G (3ULL << 4) This one is already defined > #define VTD_INV_DESC_PIOTLB_RSVD_VAL0 0xfff000000000ffc0ULL > #define VTD_INV_DESC_PIOTLB_RSVD_VAL1 0xf80ULL > - > #define VTD_INV_DESC_PIOTLB_PASID(val) (((val) >> 32) & 0xfffffULL) > #define VTD_INV_DESC_PIOTLB_DID(val) (((val) >> 16) & \ > VTD_DOMAIN_ID_MASK) > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c > index 0733180501..9dd41b835b 100644 > --- a/hw/i386/intel_iommu.c > +++ b/hw/i386/intel_iommu.c > @@ -3708,8 +3708,9 @@ static bool vtd_process_piotlb_desc(IntelIOMMUState *s, > > if ((inv_desc->val[0] & VTD_INV_DESC_PIOTLB_RSVD_VAL0) || > (inv_desc->val[1] & VTD_INV_DESC_PIOTLB_RSVD_VAL1)) { > - error_report_once("non-zero-field-in-piotlb_inv_desc hi: 0x%" PRIx64 > - " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]); > + error_report_once("%s: invalid piotlb inv desc hi=0x%"PRIx64 > + " lo=0x%"PRIx64" (reserved bits unzero)", > + __func__, inv_desc->val[1], inv_desc->val[0]); > return false; > } lgtm > > @@ -3728,8 +3729,10 @@ static bool vtd_process_piotlb_desc(IntelIOMMUState *s, > break; > > default: > - error_report_once("Invalid granularity in P-IOTLB desc hi: 0x%" PRIx64 > - " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]); > + error_report_once("%s: invalid piotlb inv desc: hi=0x%"PRIx64 > + ", lo=0x%"PRIx64" (type mismatch: 0x%llx)", > + __func__, inv_desc->val[1], inv_desc->val[0], > + inv_desc->val[0] & VTD_INV_DESC_IOTLB_G); > return false; > } > return true; lgtm > > Thanks > Zhenzhong Thanks >cmd
>-----Original Message----- >From: CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com> >Subject: Re: [PATCH v1 04/17] intel_iommu: Flush stage-2 cache in PADID- >selective PASID-based iotlb invalidation > > > >On 24/07/2024 04:59, Duan, Zhenzhong wrote: >> Caution: External email. Do not open attachments or click links, unless this >email comes from a known sender and you know the content is safe. >> >> >>> -----Original Message----- >>> From: CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com> >>> Subject: Re: [PATCH v1 04/17] intel_iommu: Flush stage-2 cache in >PADID- >>> selective PASID-based iotlb invalidation >>> >>> >>> >>> On 18/07/2024 10:16, Zhenzhong Duan wrote: >>>> Caution: External email. Do not open attachments or click links, unless >this >>> email comes from a known sender and you know the content is safe. >>>> >>>> Per spec 6.5.2.4, PADID-selective PASID-based iotlb invalidation will >>>> flush stage-2 iotlb entries with matching domain id and pasid. >>>> >>>> With scalable modern mode introduced, guest could send PASID- >selective >>>> PASID-based iotlb invalidation to flush both stage-1 and stage-2 entries. >>>> >>>> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> >>>> --- >>>> hw/i386/intel_iommu_internal.h | 10 +++++ >>>> hw/i386/intel_iommu.c | 78 >>> ++++++++++++++++++++++++++++++++++ >>>> 2 files changed, 88 insertions(+) >>>> >>>> diff --git a/hw/i386/intel_iommu_internal.h >>> b/hw/i386/intel_iommu_internal.h >>>> index 4e0331caba..f71fc91234 100644 >>>> --- a/hw/i386/intel_iommu_internal.h >>>> +++ b/hw/i386/intel_iommu_internal.h >>>> @@ -440,6 +440,16 @@ typedef union VTDInvDesc VTDInvDesc; >>>> (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | >>> VTD_SL_TM)) : \ >>>> (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) >>>> >>>> +#define VTD_INV_DESC_PIOTLB_ALL_IN_PASID (2ULL << 4) >>>> +#define VTD_INV_DESC_PIOTLB_PSI_IN_PASID (3ULL << 4) >>>> + >>>> +#define VTD_INV_DESC_PIOTLB_RSVD_VAL0 0xfff000000000ffc0ULL >>>> +#define VTD_INV_DESC_PIOTLB_RSVD_VAL1 0xf80ULL >>>> + >>>> +#define VTD_INV_DESC_PIOTLB_PASID(val) (((val) >> 32) & 0xfffffULL) >>>> +#define VTD_INV_DESC_PIOTLB_DID(val) (((val) >> 16) & \ >>>> + VTD_DOMAIN_ID_MASK) >>>> + >>>> /* Information about page-selective IOTLB invalidate */ >>>> struct VTDIOTLBPageInvInfo { >>>> uint16_t domain_id; >>>> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c >>>> index 40cbd4a0f4..075a27adac 100644 >>>> --- a/hw/i386/intel_iommu.c >>>> +++ b/hw/i386/intel_iommu.c >>>> @@ -2659,6 +2659,80 @@ static bool >>> vtd_process_iotlb_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) >>>> return true; >>>> } >>>> >>>> +static gboolean vtd_hash_remove_by_pasid(gpointer key, gpointer >value, >>>> + gpointer user_data) >>>> +{ >>>> + VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value; >>>> + VTDIOTLBPageInvInfo *info = (VTDIOTLBPageInvInfo *)user_data; >>>> + >>>> + return ((entry->domain_id == info->domain_id) && >>>> + (entry->pasid == info->pasid)); >>>> +} >>>> + >>>> +static void vtd_piotlb_pasid_invalidate(IntelIOMMUState *s, >>>> + uint16_t domain_id, uint32_t pasid) >>>> +{ >>>> + VTDIOTLBPageInvInfo info; >>>> + VTDAddressSpace *vtd_as; >>>> + VTDContextEntry ce; >>>> + >>>> + info.domain_id = domain_id; >>>> + info.pasid = pasid; >>>> + >>>> + vtd_iommu_lock(s); >>>> + g_hash_table_foreach_remove(s->iotlb, >vtd_hash_remove_by_pasid, >>>> + &info); >>>> + vtd_iommu_unlock(s); >>>> + >>>> + QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) { >>>> + if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), >>>> + vtd_as->devfn, &ce) && >>>> + domain_id == vtd_get_domain_id(s, &ce, vtd_as->pasid)) { >>>> + uint32_t rid2pasid = VTD_CE_GET_RID2PASID(&ce); >>>> + >>>> + if ((vtd_as->pasid != PCI_NO_PASID || pasid != rid2pasid) && >>>> + vtd_as->pasid != pasid) { >>>> + continue; >>>> + } >>>> + >>>> + if (!s->scalable_modern) { >>>> + vtd_address_space_sync(vtd_as); >>>> + } >>>> + } >>>> + } >>>> +} >>>> + >>>> +static bool vtd_process_piotlb_desc(IntelIOMMUState *s, >>>> + VTDInvDesc *inv_desc) >>>> +{ >>>> + uint16_t domain_id; >>>> + uint32_t pasid; >>>> + >>>> + if ((inv_desc->val[0] & VTD_INV_DESC_PIOTLB_RSVD_VAL0) || >>>> + (inv_desc->val[1] & VTD_INV_DESC_PIOTLB_RSVD_VAL1)) { >>>> + error_report_once("non-zero-field-in-piotlb_inv_desc hi: 0x%" >>> PRIx64 >>>> + " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]); >>> This error is not formatted as the other similar messages we print when >>> reserved bits are non-zero. >>> Here is what we've done in vtd_process_iotlb_desc: >> Sure, will change as below, >> >>> error_report_once("%s: invalid iotlb inv desc: hi=0x%"PRIx64 >>> ", lo=0x%"PRIx64" (reserved bits unzero)", >>> __func__, inv_desc->hi, inv_desc->lo); >>>> + return false; >>>> + } >>>> + >>>> + domain_id = VTD_INV_DESC_PIOTLB_DID(inv_desc->val[0]); >>>> + pasid = VTD_INV_DESC_PIOTLB_PASID(inv_desc->val[0]); >>>> + switch (inv_desc->val[0] & VTD_INV_DESC_IOTLB_G) { >>> Not critical but why don't we have VTD_INV_DESC_PIOTLB_G? >> Will add. >> >>>> + case VTD_INV_DESC_PIOTLB_ALL_IN_PASID: >>>> + vtd_piotlb_pasid_invalidate(s, domain_id, pasid); >>>> + break; >>>> + >>>> + case VTD_INV_DESC_PIOTLB_PSI_IN_PASID: >>>> + break; >>>> + >>>> + default: >>>> + error_report_once("Invalid granularity in P-IOTLB desc hi: 0x%" >>> PRIx64 >>>> + " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]); >>> Same comment, I think we should make the messages consistent across >>> descriptor handlers. >> What about below: >> >> diff --git a/hw/i386/intel_iommu_internal.h >b/hw/i386/intel_iommu_internal.h >> index 3290761595..e76fd9d377 100644 >> --- a/hw/i386/intel_iommu_internal.h >> +++ b/hw/i386/intel_iommu_internal.h >> @@ -479,9 +479,10 @@ typedef union VTDInvDesc VTDInvDesc; >> #define VTD_INV_DESC_PIOTLB_ALL_IN_PASID (2ULL << 4) >> #define VTD_INV_DESC_PIOTLB_PSI_IN_PASID (3ULL << 4) >> >> +/* Masks for IOTLB Invalidate Descriptor */ >> +#define VTD_INV_DESC_IOTLB_G (3ULL << 4) >This one is already defined Ah, typo, I mean: +#define VTD_INV_DESC_PIOTLB_G (3ULL << 4) Thanks Zhenzhong
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 4e0331caba..f71fc91234 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -440,6 +440,16 @@ typedef union VTDInvDesc VTDInvDesc; (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \ (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) +#define VTD_INV_DESC_PIOTLB_ALL_IN_PASID (2ULL << 4) +#define VTD_INV_DESC_PIOTLB_PSI_IN_PASID (3ULL << 4) + +#define VTD_INV_DESC_PIOTLB_RSVD_VAL0 0xfff000000000ffc0ULL +#define VTD_INV_DESC_PIOTLB_RSVD_VAL1 0xf80ULL + +#define VTD_INV_DESC_PIOTLB_PASID(val) (((val) >> 32) & 0xfffffULL) +#define VTD_INV_DESC_PIOTLB_DID(val) (((val) >> 16) & \ + VTD_DOMAIN_ID_MASK) + /* Information about page-selective IOTLB invalidate */ struct VTDIOTLBPageInvInfo { uint16_t domain_id; diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 40cbd4a0f4..075a27adac 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2659,6 +2659,80 @@ static bool vtd_process_iotlb_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) return true; } +static gboolean vtd_hash_remove_by_pasid(gpointer key, gpointer value, + gpointer user_data) +{ + VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value; + VTDIOTLBPageInvInfo *info = (VTDIOTLBPageInvInfo *)user_data; + + return ((entry->domain_id == info->domain_id) && + (entry->pasid == info->pasid)); +} + +static void vtd_piotlb_pasid_invalidate(IntelIOMMUState *s, + uint16_t domain_id, uint32_t pasid) +{ + VTDIOTLBPageInvInfo info; + VTDAddressSpace *vtd_as; + VTDContextEntry ce; + + info.domain_id = domain_id; + info.pasid = pasid; + + vtd_iommu_lock(s); + g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_pasid, + &info); + vtd_iommu_unlock(s); + + QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) { + if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), + vtd_as->devfn, &ce) && + domain_id == vtd_get_domain_id(s, &ce, vtd_as->pasid)) { + uint32_t rid2pasid = VTD_CE_GET_RID2PASID(&ce); + + if ((vtd_as->pasid != PCI_NO_PASID || pasid != rid2pasid) && + vtd_as->pasid != pasid) { + continue; + } + + if (!s->scalable_modern) { + vtd_address_space_sync(vtd_as); + } + } + } +} + +static bool vtd_process_piotlb_desc(IntelIOMMUState *s, + VTDInvDesc *inv_desc) +{ + uint16_t domain_id; + uint32_t pasid; + + if ((inv_desc->val[0] & VTD_INV_DESC_PIOTLB_RSVD_VAL0) || + (inv_desc->val[1] & VTD_INV_DESC_PIOTLB_RSVD_VAL1)) { + error_report_once("non-zero-field-in-piotlb_inv_desc hi: 0x%" PRIx64 + " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]); + return false; + } + + domain_id = VTD_INV_DESC_PIOTLB_DID(inv_desc->val[0]); + pasid = VTD_INV_DESC_PIOTLB_PASID(inv_desc->val[0]); + switch (inv_desc->val[0] & VTD_INV_DESC_IOTLB_G) { + case VTD_INV_DESC_PIOTLB_ALL_IN_PASID: + vtd_piotlb_pasid_invalidate(s, domain_id, pasid); + break; + + case VTD_INV_DESC_PIOTLB_PSI_IN_PASID: + break; + + default: + error_report_once("Invalid granularity in P-IOTLB desc hi: 0x%" PRIx64 + " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]); + return false; + } + return true; +} + static bool vtd_process_inv_iec_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) { @@ -2769,6 +2843,10 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s) break; case VTD_INV_DESC_PIOTLB: + trace_vtd_inv_desc("p-iotlb", inv_desc.val[1], inv_desc.val[0]); + if (!vtd_process_piotlb_desc(s, &inv_desc)) { + return false; + } break; case VTD_INV_DESC_WAIT:
Per spec 6.5.2.4, PADID-selective PASID-based iotlb invalidation will flush stage-2 iotlb entries with matching domain id and pasid. With scalable modern mode introduced, guest could send PASID-selective PASID-based iotlb invalidation to flush both stage-1 and stage-2 entries. Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> --- hw/i386/intel_iommu_internal.h | 10 +++++ hw/i386/intel_iommu.c | 78 ++++++++++++++++++++++++++++++++++ 2 files changed, 88 insertions(+)