| Message ID | 20240708173501.426225-6-dbarboza@ventanamicro.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv: QEMU RISC-V IOMMU Support | expand |
On Tue, Jul 9, 2024 at 3:38 AM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > From: Tomasz Jeznach <tjeznach@rivosinc.com> > > The RISC-V IOMMU can be modelled as a PCIe device following the > guidelines of the RISC-V IOMMU spec, chapter 7.1, "Integrating an IOMMU > as a PCIe device". > > Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > hw/riscv/meson.build | 2 +- > hw/riscv/riscv-iommu-pci.c | 178 +++++++++++++++++++++++++++++++++++++ > 2 files changed, 179 insertions(+), 1 deletion(-) > create mode 100644 hw/riscv/riscv-iommu-pci.c > > diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build > index cbc99c6e8e..adbef8a9b2 100644 > --- a/hw/riscv/meson.build > +++ b/hw/riscv/meson.build > @@ -10,6 +10,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) > riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) > riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c')) > riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c')) > -riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c')) > +riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c', 'riscv-iommu-pci.c')) > > hw_arch += {'riscv': riscv_ss} > diff --git a/hw/riscv/riscv-iommu-pci.c b/hw/riscv/riscv-iommu-pci.c > new file mode 100644 > index 0000000000..7b82ce0645 > --- /dev/null > +++ b/hw/riscv/riscv-iommu-pci.c > @@ -0,0 +1,178 @@ > +/* > + * QEMU emulation of an RISC-V IOMMU > + * > + * Copyright (C) 2022-2023 Rivos Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, see <http://www.gnu.org/licenses/>. > + */ > + > +#include "qemu/osdep.h" > +#include "hw/pci/msi.h" > +#include "hw/pci/msix.h" > +#include "hw/pci/pci_bus.h" > +#include "hw/qdev-properties.h" > +#include "hw/riscv/riscv_hart.h" > +#include "migration/vmstate.h" > +#include "qapi/error.h" > +#include "qemu/error-report.h" > +#include "qemu/host-utils.h" > +#include "qom/object.h" > + > +#include "cpu_bits.h" > +#include "riscv-iommu.h" > +#include "riscv-iommu-bits.h" > + > +/* RISC-V IOMMU PCI Device Emulation */ > +#define RISCV_PCI_CLASS_SYSTEM_IOMMU 0x0806 > + > +typedef struct RISCVIOMMUStatePci { > + PCIDevice pci; /* Parent PCIe device state */ > + uint16_t vendor_id; > + uint16_t device_id; > + uint8_t revision; > + MemoryRegion bar0; /* PCI BAR (including MSI-x config) */ > + RISCVIOMMUState iommu; /* common IOMMU state */ > +} RISCVIOMMUStatePci; > + > +/* interrupt delivery callback */ > +static void riscv_iommu_pci_notify(RISCVIOMMUState *iommu, unsigned vector) > +{ > + RISCVIOMMUStatePci *s = container_of(iommu, RISCVIOMMUStatePci, iommu); > + > + if (msix_enabled(&(s->pci))) { > + msix_notify(&(s->pci), vector); > + } > +} > + > +static void riscv_iommu_pci_realize(PCIDevice *dev, Error **errp) > +{ > + RISCVIOMMUStatePci *s = DO_UPCAST(RISCVIOMMUStatePci, pci, dev); > + RISCVIOMMUState *iommu = &s->iommu; > + uint8_t *pci_conf = dev->config; > + Error *err = NULL; > + > + pci_set_word(pci_conf + PCI_VENDOR_ID, s->vendor_id); > + pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, s->vendor_id); > + pci_set_word(pci_conf + PCI_DEVICE_ID, s->device_id); > + pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, s->device_id); > + pci_set_byte(pci_conf + PCI_REVISION_ID, s->revision); > + > + /* Set device id for trace / debug */ > + DEVICE(iommu)->id = g_strdup_printf("%02x:%02x.%01x", > + pci_dev_bus_num(dev), PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); > + qdev_realize(DEVICE(iommu), NULL, errp); > + > + memory_region_init(&s->bar0, OBJECT(s), "riscv-iommu-bar0", > + QEMU_ALIGN_UP(memory_region_size(&iommu->regs_mr), TARGET_PAGE_SIZE)); > + memory_region_add_subregion(&s->bar0, 0, &iommu->regs_mr); > + > + pcie_endpoint_cap_init(dev, 0); > + > + pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | > + PCI_BASE_ADDRESS_MEM_TYPE_64, &s->bar0); > + > + int ret = msix_init(dev, RISCV_IOMMU_INTR_COUNT, > + &s->bar0, 0, RISCV_IOMMU_REG_MSI_CONFIG, > + &s->bar0, 0, RISCV_IOMMU_REG_MSI_CONFIG + 256, 0, &err); > + > + if (ret == -ENOTSUP) { > + /* > + * MSI-x is not supported by the platform. > + * Driver should use timer/polling based notification handlers. > + */ > + warn_report_err(err); > + } else if (ret < 0) { > + error_propagate(errp, err); > + return; > + } else { > + /* mark all allocated MSIx vectors as used. */ > + msix_vector_use(dev, RISCV_IOMMU_INTR_CQ); > + msix_vector_use(dev, RISCV_IOMMU_INTR_FQ); > + msix_vector_use(dev, RISCV_IOMMU_INTR_PM); > + msix_vector_use(dev, RISCV_IOMMU_INTR_PQ); > + iommu->notify = riscv_iommu_pci_notify; > + } > + > + PCIBus *bus = pci_device_root_bus(dev); > + if (!bus) { > + error_setg(errp, "can't find PCIe root port for %02x:%02x.%x", > + pci_bus_num(pci_get_bus(dev)), PCI_SLOT(dev->devfn), > + PCI_FUNC(dev->devfn)); > + return; > + } > + > + riscv_iommu_pci_setup_iommu(iommu, bus, errp); > +} > + > +static void riscv_iommu_pci_exit(PCIDevice *pci_dev) > +{ > + pci_setup_iommu(pci_device_root_bus(pci_dev), NULL, NULL); > +} > + > +static const VMStateDescription riscv_iommu_vmstate = { > + .name = "riscv-iommu", > + .unmigratable = 1 > +}; > + > +static void riscv_iommu_pci_init(Object *obj) > +{ > + RISCVIOMMUStatePci *s = RISCV_IOMMU_PCI(obj); > + RISCVIOMMUState *iommu = &s->iommu; > + > + object_initialize_child(obj, "iommu", iommu, TYPE_RISCV_IOMMU); > + qdev_alias_all_properties(DEVICE(iommu), obj); > +} > + > +static Property riscv_iommu_pci_properties[] = { > + DEFINE_PROP_UINT16("vendor-id", RISCVIOMMUStatePci, vendor_id, > + PCI_VENDOR_ID_REDHAT), > + DEFINE_PROP_UINT16("device-id", RISCVIOMMUStatePci, device_id, > + PCI_DEVICE_ID_REDHAT_RISCV_IOMMU), > + DEFINE_PROP_UINT8("revision", RISCVIOMMUStatePci, revision, 0x01), > + DEFINE_PROP_END_OF_LIST(), > +}; > + > +static void riscv_iommu_pci_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(klass); > + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); > + > + k->realize = riscv_iommu_pci_realize; > + k->exit = riscv_iommu_pci_exit; > + k->class_id = RISCV_PCI_CLASS_SYSTEM_IOMMU; > + dc->desc = "RISCV-IOMMU DMA Remapping device"; > + dc->vmsd = &riscv_iommu_vmstate; > + dc->hotpluggable = false; > + dc->user_creatable = true; > + set_bit(DEVICE_CATEGORY_MISC, dc->categories); > + device_class_set_props(dc, riscv_iommu_pci_properties); > +} > + > +static const TypeInfo riscv_iommu_pci = { > + .name = TYPE_RISCV_IOMMU_PCI, > + .parent = TYPE_PCI_DEVICE, > + .class_init = riscv_iommu_pci_class_init, > + .instance_init = riscv_iommu_pci_init, > + .instance_size = sizeof(RISCVIOMMUStatePci), > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_PCIE_DEVICE }, > + { }, > + }, > +}; > + > +static void riscv_iommu_register_pci_types(void) > +{ > + type_register_static(&riscv_iommu_pci); > +} > + > +type_init(riscv_iommu_register_pci_types); > -- > 2.45.2 > >
Hi Daniel, On 2024/7/9 上午 01:34, Daniel Henrique Barboza wrote: > From: Tomasz Jeznach <tjeznach@rivosinc.com> > > The RISC-V IOMMU can be modelled as a PCIe device following the > guidelines of the RISC-V IOMMU spec, chapter 7.1, "Integrating an IOMMU > as a PCIe device". > > Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > Reviewed-by: Frank Chang <frank.chang@sifive.com> > --- > hw/riscv/meson.build | 2 +- > hw/riscv/riscv-iommu-pci.c | 178 +++++++++++++++++++++++++++++++++++++ > 2 files changed, 179 insertions(+), 1 deletion(-) > create mode 100644 hw/riscv/riscv-iommu-pci.c > > diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build > index cbc99c6e8e..adbef8a9b2 100644 > --- a/hw/riscv/meson.build > +++ b/hw/riscv/meson.build > @@ -10,6 +10,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) > riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) > riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c')) > riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c')) > -riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c')) > +riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c', 'riscv-iommu-pci.c')) > > hw_arch += {'riscv': riscv_ss} > diff --git a/hw/riscv/riscv-iommu-pci.c b/hw/riscv/riscv-iommu-pci.c > new file mode 100644 > index 0000000000..7b82ce0645 > --- /dev/null > +++ b/hw/riscv/riscv-iommu-pci.c > @@ -0,0 +1,178 @@ > +/* > + * QEMU emulation of an RISC-V IOMMU > + * > + * Copyright (C) 2022-2023 Rivos Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, see <http://www.gnu.org/licenses/>. > + */ > + > +#include "qemu/osdep.h" > +#include "hw/pci/msi.h" > +#include "hw/pci/msix.h" > +#include "hw/pci/pci_bus.h" > +#include "hw/qdev-properties.h" > +#include "hw/riscv/riscv_hart.h" > +#include "migration/vmstate.h" > +#include "qapi/error.h" > +#include "qemu/error-report.h" > +#include "qemu/host-utils.h" > +#include "qom/object.h" > + > +#include "cpu_bits.h" > +#include "riscv-iommu.h" > +#include "riscv-iommu-bits.h" > + > +/* RISC-V IOMMU PCI Device Emulation */ > +#define RISCV_PCI_CLASS_SYSTEM_IOMMU 0x0806 > + > +typedef struct RISCVIOMMUStatePci { > + PCIDevice pci; /* Parent PCIe device state */ > + uint16_t vendor_id; > + uint16_t device_id; > + uint8_t revision; > + MemoryRegion bar0; /* PCI BAR (including MSI-x config) */ > + RISCVIOMMUState iommu; /* common IOMMU state */ > +} RISCVIOMMUStatePci; > + > +/* interrupt delivery callback */ > +static void riscv_iommu_pci_notify(RISCVIOMMUState *iommu, unsigned vector) > +{ > + RISCVIOMMUStatePci *s = container_of(iommu, RISCVIOMMUStatePci, iommu); > + > + if (msix_enabled(&(s->pci))) { > + msix_notify(&(s->pci), vector); > + } > +} > + > +static void riscv_iommu_pci_realize(PCIDevice *dev, Error **errp) > +{ > + RISCVIOMMUStatePci *s = DO_UPCAST(RISCVIOMMUStatePci, pci, dev); > + RISCVIOMMUState *iommu = &s->iommu; > + uint8_t *pci_conf = dev->config; > + Error *err = NULL; > + > + pci_set_word(pci_conf + PCI_VENDOR_ID, s->vendor_id); > + pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, s->vendor_id); > + pci_set_word(pci_conf + PCI_DEVICE_ID, s->device_id); > + pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, s->device_id); > + pci_set_byte(pci_conf + PCI_REVISION_ID, s->revision); > + > + /* Set device id for trace / debug */ > + DEVICE(iommu)->id = g_strdup_printf("%02x:%02x.%01x", > + pci_dev_bus_num(dev), PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); > + qdev_realize(DEVICE(iommu), NULL, errp); > + > + memory_region_init(&s->bar0, OBJECT(s), "riscv-iommu-bar0", > + QEMU_ALIGN_UP(memory_region_size(&iommu->regs_mr), TARGET_PAGE_SIZE)); > + memory_region_add_subregion(&s->bar0, 0, &iommu->regs_mr); > + > + pcie_endpoint_cap_init(dev, 0); > + > + pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | > + PCI_BASE_ADDRESS_MEM_TYPE_64, &s->bar0); > + > + int ret = msix_init(dev, RISCV_IOMMU_INTR_COUNT, > + &s->bar0, 0, RISCV_IOMMU_REG_MSI_CONFIG, > + &s->bar0, 0, RISCV_IOMMU_REG_MSI_CONFIG + 256, 0, &err); > + > + if (ret == -ENOTSUP) { > + /* > + * MSI-x is not supported by the platform. > + * Driver should use timer/polling based notification handlers. > + */ > + warn_report_err(err); > + } else if (ret < 0) { > + error_propagate(errp, err); > + return; > + } else { > + /* mark all allocated MSIx vectors as used. */ > + msix_vector_use(dev, RISCV_IOMMU_INTR_CQ); > + msix_vector_use(dev, RISCV_IOMMU_INTR_FQ); > + msix_vector_use(dev, RISCV_IOMMU_INTR_PM); > + msix_vector_use(dev, RISCV_IOMMU_INTR_PQ); In ICVEC register, each interrupt cause has a 4-bit field, which can be configured with values within 0 to 15. We only allow vector values being 0 to 3 here, but software may want to use other vector number. > + iommu->notify = riscv_iommu_pci_notify; > + } > + > + PCIBus *bus = pci_device_root_bus(dev); > + if (!bus) { > + error_setg(errp, "can't find PCIe root port for %02x:%02x.%x", > + pci_bus_num(pci_get_bus(dev)), PCI_SLOT(dev->devfn), > + PCI_FUNC(dev->devfn)); > + return; > + } > + > + riscv_iommu_pci_setup_iommu(iommu, bus, errp); > +} > + > +static void riscv_iommu_pci_exit(PCIDevice *pci_dev) > +{ > + pci_setup_iommu(pci_device_root_bus(pci_dev), NULL, NULL); > +} > + > +static const VMStateDescription riscv_iommu_vmstate = { > + .name = "riscv-iommu", > + .unmigratable = 1 > +}; > + > +static void riscv_iommu_pci_init(Object *obj) > +{ > + RISCVIOMMUStatePci *s = RISCV_IOMMU_PCI(obj); > + RISCVIOMMUState *iommu = &s->iommu; > + > + object_initialize_child(obj, "iommu", iommu, TYPE_RISCV_IOMMU); > + qdev_alias_all_properties(DEVICE(iommu), obj); > +} > + > +static Property riscv_iommu_pci_properties[] = { > + DEFINE_PROP_UINT16("vendor-id", RISCVIOMMUStatePci, vendor_id, > + PCI_VENDOR_ID_REDHAT), > + DEFINE_PROP_UINT16("device-id", RISCVIOMMUStatePci, device_id, > + PCI_DEVICE_ID_REDHAT_RISCV_IOMMU), > + DEFINE_PROP_UINT8("revision", RISCVIOMMUStatePci, revision, 0x01), > + DEFINE_PROP_END_OF_LIST(), > +}; > + > +static void riscv_iommu_pci_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(klass); > + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); > + > + k->realize = riscv_iommu_pci_realize; > + k->exit = riscv_iommu_pci_exit; > + k->class_id = RISCV_PCI_CLASS_SYSTEM_IOMMU; > + dc->desc = "RISCV-IOMMU DMA Remapping device"; > + dc->vmsd = &riscv_iommu_vmstate; > + dc->hotpluggable = false; > + dc->user_creatable = true; > + set_bit(DEVICE_CATEGORY_MISC, dc->categories); > + device_class_set_props(dc, riscv_iommu_pci_properties); > +} > + > +static const TypeInfo riscv_iommu_pci = { > + .name = TYPE_RISCV_IOMMU_PCI, > + .parent = TYPE_PCI_DEVICE, > + .class_init = riscv_iommu_pci_class_init, > + .instance_init = riscv_iommu_pci_init, > + .instance_size = sizeof(RISCVIOMMUStatePci), > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_PCIE_DEVICE }, > + { }, > + }, > +}; > + > +static void riscv_iommu_register_pci_types(void) > +{ > + type_register_static(&riscv_iommu_pci); > +} > + > +type_init(riscv_iommu_register_pci_types);
On 7/18/24 4:06 AM, Jason Chien wrote: > Hi Daniel, > > On 2024/7/9 上午 01:34, Daniel Henrique Barboza wrote: >> From: Tomasz Jeznach <tjeznach@rivosinc.com> >> >> The RISC-V IOMMU can be modelled as a PCIe device following the >> guidelines of the RISC-V IOMMU spec, chapter 7.1, "Integrating an IOMMU >> as a PCIe device". >> >> Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> >> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> >> Reviewed-by: Frank Chang <frank.chang@sifive.com> >> --- >> hw/riscv/meson.build | 2 +- >> hw/riscv/riscv-iommu-pci.c | 178 +++++++++++++++++++++++++++++++++++++ >> 2 files changed, 179 insertions(+), 1 deletion(-) >> create mode 100644 hw/riscv/riscv-iommu-pci.c >> >> diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build >> index cbc99c6e8e..adbef8a9b2 100644 >> --- a/hw/riscv/meson.build >> +++ b/hw/riscv/meson.build >> @@ -10,6 +10,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) >> riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) >> riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c')) >> riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c')) >> -riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c')) >> +riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c', 'riscv-iommu-pci.c')) >> hw_arch += {'riscv': riscv_ss} >> diff --git a/hw/riscv/riscv-iommu-pci.c b/hw/riscv/riscv-iommu-pci.c >> new file mode 100644 >> index 0000000000..7b82ce0645 >> --- /dev/null >> +++ b/hw/riscv/riscv-iommu-pci.c >> @@ -0,0 +1,178 @@ >> +/* >> + * QEMU emulation of an RISC-V IOMMU >> + * >> + * Copyright (C) 2022-2023 Rivos Inc. >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License as published by >> + * the Free Software Foundation; either version 2 of the License. >> + * >> + * This program is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + * >> + * You should have received a copy of the GNU General Public License along >> + * with this program; if not, see <http://www.gnu.org/licenses/>. >> + */ >> + >> +#include "qemu/osdep.h" >> +#include "hw/pci/msi.h" >> +#include "hw/pci/msix.h" >> +#include "hw/pci/pci_bus.h" >> +#include "hw/qdev-properties.h" >> +#include "hw/riscv/riscv_hart.h" >> +#include "migration/vmstate.h" >> +#include "qapi/error.h" >> +#include "qemu/error-report.h" >> +#include "qemu/host-utils.h" >> +#include "qom/object.h" >> + >> +#include "cpu_bits.h" >> +#include "riscv-iommu.h" >> +#include "riscv-iommu-bits.h" >> + >> +/* RISC-V IOMMU PCI Device Emulation */ >> +#define RISCV_PCI_CLASS_SYSTEM_IOMMU 0x0806 >> + >> +typedef struct RISCVIOMMUStatePci { >> + PCIDevice pci; /* Parent PCIe device state */ >> + uint16_t vendor_id; >> + uint16_t device_id; >> + uint8_t revision; >> + MemoryRegion bar0; /* PCI BAR (including MSI-x config) */ >> + RISCVIOMMUState iommu; /* common IOMMU state */ >> +} RISCVIOMMUStatePci; >> + >> +/* interrupt delivery callback */ >> +static void riscv_iommu_pci_notify(RISCVIOMMUState *iommu, unsigned vector) >> +{ >> + RISCVIOMMUStatePci *s = container_of(iommu, RISCVIOMMUStatePci, iommu); >> + >> + if (msix_enabled(&(s->pci))) { >> + msix_notify(&(s->pci), vector); >> + } >> +} >> + >> +static void riscv_iommu_pci_realize(PCIDevice *dev, Error **errp) >> +{ >> + RISCVIOMMUStatePci *s = DO_UPCAST(RISCVIOMMUStatePci, pci, dev); >> + RISCVIOMMUState *iommu = &s->iommu; >> + uint8_t *pci_conf = dev->config; >> + Error *err = NULL; >> + >> + pci_set_word(pci_conf + PCI_VENDOR_ID, s->vendor_id); >> + pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, s->vendor_id); >> + pci_set_word(pci_conf + PCI_DEVICE_ID, s->device_id); >> + pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, s->device_id); >> + pci_set_byte(pci_conf + PCI_REVISION_ID, s->revision); >> + >> + /* Set device id for trace / debug */ >> + DEVICE(iommu)->id = g_strdup_printf("%02x:%02x.%01x", >> + pci_dev_bus_num(dev), PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); >> + qdev_realize(DEVICE(iommu), NULL, errp); >> + >> + memory_region_init(&s->bar0, OBJECT(s), "riscv-iommu-bar0", >> + QEMU_ALIGN_UP(memory_region_size(&iommu->regs_mr), TARGET_PAGE_SIZE)); >> + memory_region_add_subregion(&s->bar0, 0, &iommu->regs_mr); >> + >> + pcie_endpoint_cap_init(dev, 0); >> + >> + pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | >> + PCI_BASE_ADDRESS_MEM_TYPE_64, &s->bar0); >> + >> + int ret = msix_init(dev, RISCV_IOMMU_INTR_COUNT, >> + &s->bar0, 0, RISCV_IOMMU_REG_MSI_CONFIG, >> + &s->bar0, 0, RISCV_IOMMU_REG_MSI_CONFIG + 256, 0, &err); >> + >> + if (ret == -ENOTSUP) { >> + /* >> + * MSI-x is not supported by the platform. >> + * Driver should use timer/polling based notification handlers. >> + */ >> + warn_report_err(err); >> + } else if (ret < 0) { >> + error_propagate(errp, err); >> + return; >> + } else { >> + /* mark all allocated MSIx vectors as used. */ >> + msix_vector_use(dev, RISCV_IOMMU_INTR_CQ); >> + msix_vector_use(dev, RISCV_IOMMU_INTR_FQ); >> + msix_vector_use(dev, RISCV_IOMMU_INTR_PM); >> + msix_vector_use(dev, RISCV_IOMMU_INTR_PQ); > In ICVEC register, each interrupt cause has a 4-bit field, which can be configured with values within 0 to 15. We only allow vector values being 0 to 3 here, but software may want to use other vector number. We need a new interface to notify IOMMU devices about icvec SW updates. I added the relevant code for it in patch 3, where a new "icvec_update" is used to inform the device (riscv-iommu-pci, and later riscv-iommu-sys) about the configuration update. In this patch I'll keep these default vals during realize because I'm not sure about how SW will behave (will it always write ICVEC?). 'icvec_update' will de-register the existing vectors and use the newer ones based updates on ICVEC. Thanks, Daniel >> + iommu->notify = riscv_iommu_pci_notify; >> + } >> + >> + PCIBus *bus = pci_device_root_bus(dev); >> + if (!bus) { >> + error_setg(errp, "can't find PCIe root port for %02x:%02x.%x", >> + pci_bus_num(pci_get_bus(dev)), PCI_SLOT(dev->devfn), >> + PCI_FUNC(dev->devfn)); >> + return; >> + } >> + >> + riscv_iommu_pci_setup_iommu(iommu, bus, errp); >> +} >> + >> +static void riscv_iommu_pci_exit(PCIDevice *pci_dev) >> +{ >> + pci_setup_iommu(pci_device_root_bus(pci_dev), NULL, NULL); >> +} >> + >> +static const VMStateDescription riscv_iommu_vmstate = { >> + .name = "riscv-iommu", >> + .unmigratable = 1 >> +}; >> + >> +static void riscv_iommu_pci_init(Object *obj) >> +{ >> + RISCVIOMMUStatePci *s = RISCV_IOMMU_PCI(obj); >> + RISCVIOMMUState *iommu = &s->iommu; >> + >> + object_initialize_child(obj, "iommu", iommu, TYPE_RISCV_IOMMU); >> + qdev_alias_all_properties(DEVICE(iommu), obj); >> +} >> + >> +static Property riscv_iommu_pci_properties[] = { >> + DEFINE_PROP_UINT16("vendor-id", RISCVIOMMUStatePci, vendor_id, >> + PCI_VENDOR_ID_REDHAT), >> + DEFINE_PROP_UINT16("device-id", RISCVIOMMUStatePci, device_id, >> + PCI_DEVICE_ID_REDHAT_RISCV_IOMMU), >> + DEFINE_PROP_UINT8("revision", RISCVIOMMUStatePci, revision, 0x01), >> + DEFINE_PROP_END_OF_LIST(), >> +}; >> + >> +static void riscv_iommu_pci_class_init(ObjectClass *klass, void *data) >> +{ >> + DeviceClass *dc = DEVICE_CLASS(klass); >> + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); >> + >> + k->realize = riscv_iommu_pci_realize; >> + k->exit = riscv_iommu_pci_exit; >> + k->class_id = RISCV_PCI_CLASS_SYSTEM_IOMMU; >> + dc->desc = "RISCV-IOMMU DMA Remapping device"; >> + dc->vmsd = &riscv_iommu_vmstate; >> + dc->hotpluggable = false; >> + dc->user_creatable = true; >> + set_bit(DEVICE_CATEGORY_MISC, dc->categories); >> + device_class_set_props(dc, riscv_iommu_pci_properties); >> +} >> + >> +static const TypeInfo riscv_iommu_pci = { >> + .name = TYPE_RISCV_IOMMU_PCI, >> + .parent = TYPE_PCI_DEVICE, >> + .class_init = riscv_iommu_pci_class_init, >> + .instance_init = riscv_iommu_pci_init, >> + .instance_size = sizeof(RISCVIOMMUStatePci), >> + .interfaces = (InterfaceInfo[]) { >> + { INTERFACE_PCIE_DEVICE }, >> + { }, >> + }, >> +}; >> + >> +static void riscv_iommu_register_pci_types(void) >> +{ >> + type_register_static(&riscv_iommu_pci); >> +} >> + >> +type_init(riscv_iommu_register_pci_types);
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index cbc99c6e8e..adbef8a9b2 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -10,6 +10,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c')) riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c')) -riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c')) +riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c', 'riscv-iommu-pci.c')) hw_arch += {'riscv': riscv_ss} diff --git a/hw/riscv/riscv-iommu-pci.c b/hw/riscv/riscv-iommu-pci.c new file mode 100644 index 0000000000..7b82ce0645 --- /dev/null +++ b/hw/riscv/riscv-iommu-pci.c @@ -0,0 +1,178 @@ +/* + * QEMU emulation of an RISC-V IOMMU + * + * Copyright (C) 2022-2023 Rivos Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "hw/pci/msi.h" +#include "hw/pci/msix.h" +#include "hw/pci/pci_bus.h" +#include "hw/qdev-properties.h" +#include "hw/riscv/riscv_hart.h" +#include "migration/vmstate.h" +#include "qapi/error.h" +#include "qemu/error-report.h" +#include "qemu/host-utils.h" +#include "qom/object.h" + +#include "cpu_bits.h" +#include "riscv-iommu.h" +#include "riscv-iommu-bits.h" + +/* RISC-V IOMMU PCI Device Emulation */ +#define RISCV_PCI_CLASS_SYSTEM_IOMMU 0x0806 + +typedef struct RISCVIOMMUStatePci { + PCIDevice pci; /* Parent PCIe device state */ + uint16_t vendor_id; + uint16_t device_id; + uint8_t revision; + MemoryRegion bar0; /* PCI BAR (including MSI-x config) */ + RISCVIOMMUState iommu; /* common IOMMU state */ +} RISCVIOMMUStatePci; + +/* interrupt delivery callback */ +static void riscv_iommu_pci_notify(RISCVIOMMUState *iommu, unsigned vector) +{ + RISCVIOMMUStatePci *s = container_of(iommu, RISCVIOMMUStatePci, iommu); + + if (msix_enabled(&(s->pci))) { + msix_notify(&(s->pci), vector); + } +} + +static void riscv_iommu_pci_realize(PCIDevice *dev, Error **errp) +{ + RISCVIOMMUStatePci *s = DO_UPCAST(RISCVIOMMUStatePci, pci, dev); + RISCVIOMMUState *iommu = &s->iommu; + uint8_t *pci_conf = dev->config; + Error *err = NULL; + + pci_set_word(pci_conf + PCI_VENDOR_ID, s->vendor_id); + pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, s->vendor_id); + pci_set_word(pci_conf + PCI_DEVICE_ID, s->device_id); + pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, s->device_id); + pci_set_byte(pci_conf + PCI_REVISION_ID, s->revision); + + /* Set device id for trace / debug */ + DEVICE(iommu)->id = g_strdup_printf("%02x:%02x.%01x", + pci_dev_bus_num(dev), PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); + qdev_realize(DEVICE(iommu), NULL, errp); + + memory_region_init(&s->bar0, OBJECT(s), "riscv-iommu-bar0", + QEMU_ALIGN_UP(memory_region_size(&iommu->regs_mr), TARGET_PAGE_SIZE)); + memory_region_add_subregion(&s->bar0, 0, &iommu->regs_mr); + + pcie_endpoint_cap_init(dev, 0); + + pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | + PCI_BASE_ADDRESS_MEM_TYPE_64, &s->bar0); + + int ret = msix_init(dev, RISCV_IOMMU_INTR_COUNT, + &s->bar0, 0, RISCV_IOMMU_REG_MSI_CONFIG, + &s->bar0, 0, RISCV_IOMMU_REG_MSI_CONFIG + 256, 0, &err); + + if (ret == -ENOTSUP) { + /* + * MSI-x is not supported by the platform. + * Driver should use timer/polling based notification handlers. + */ + warn_report_err(err); + } else if (ret < 0) { + error_propagate(errp, err); + return; + } else { + /* mark all allocated MSIx vectors as used. */ + msix_vector_use(dev, RISCV_IOMMU_INTR_CQ); + msix_vector_use(dev, RISCV_IOMMU_INTR_FQ); + msix_vector_use(dev, RISCV_IOMMU_INTR_PM); + msix_vector_use(dev, RISCV_IOMMU_INTR_PQ); + iommu->notify = riscv_iommu_pci_notify; + } + + PCIBus *bus = pci_device_root_bus(dev); + if (!bus) { + error_setg(errp, "can't find PCIe root port for %02x:%02x.%x", + pci_bus_num(pci_get_bus(dev)), PCI_SLOT(dev->devfn), + PCI_FUNC(dev->devfn)); + return; + } + + riscv_iommu_pci_setup_iommu(iommu, bus, errp); +} + +static void riscv_iommu_pci_exit(PCIDevice *pci_dev) +{ + pci_setup_iommu(pci_device_root_bus(pci_dev), NULL, NULL); +} + +static const VMStateDescription riscv_iommu_vmstate = { + .name = "riscv-iommu", + .unmigratable = 1 +}; + +static void riscv_iommu_pci_init(Object *obj) +{ + RISCVIOMMUStatePci *s = RISCV_IOMMU_PCI(obj); + RISCVIOMMUState *iommu = &s->iommu; + + object_initialize_child(obj, "iommu", iommu, TYPE_RISCV_IOMMU); + qdev_alias_all_properties(DEVICE(iommu), obj); +} + +static Property riscv_iommu_pci_properties[] = { + DEFINE_PROP_UINT16("vendor-id", RISCVIOMMUStatePci, vendor_id, + PCI_VENDOR_ID_REDHAT), + DEFINE_PROP_UINT16("device-id", RISCVIOMMUStatePci, device_id, + PCI_DEVICE_ID_REDHAT_RISCV_IOMMU), + DEFINE_PROP_UINT8("revision", RISCVIOMMUStatePci, revision, 0x01), + DEFINE_PROP_END_OF_LIST(), +}; + +static void riscv_iommu_pci_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + + k->realize = riscv_iommu_pci_realize; + k->exit = riscv_iommu_pci_exit; + k->class_id = RISCV_PCI_CLASS_SYSTEM_IOMMU; + dc->desc = "RISCV-IOMMU DMA Remapping device"; + dc->vmsd = &riscv_iommu_vmstate; + dc->hotpluggable = false; + dc->user_creatable = true; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); + device_class_set_props(dc, riscv_iommu_pci_properties); +} + +static const TypeInfo riscv_iommu_pci = { + .name = TYPE_RISCV_IOMMU_PCI, + .parent = TYPE_PCI_DEVICE, + .class_init = riscv_iommu_pci_class_init, + .instance_init = riscv_iommu_pci_init, + .instance_size = sizeof(RISCVIOMMUStatePci), + .interfaces = (InterfaceInfo[]) { + { INTERFACE_PCIE_DEVICE }, + { }, + }, +}; + +static void riscv_iommu_register_pci_types(void) +{ + type_register_static(&riscv_iommu_pci); +} + +type_init(riscv_iommu_register_pci_types);