Message ID | 20240725072117.22425-1-quic_qqzhou@quicinc.com (mailing list archive) |
---|---|
State | Accepted |
Commit | 421688265d7f5d3ff4211982e7231765378bb64f |
Headers | show |
Series | [v3] arm64: dts: qcom: sa8775p: Mark APPS and PCIe SMMUs as DMA coherent | expand |
On Thu, 25 Jul 2024 12:51:17 +0530, Qingqing Zhou wrote: > The SMMUs on sa8775p are cache-coherent. GPU SMMU is marked as such, > mark the APPS and PCIe ones as well. > > Applied, thanks! [1/1] arm64: dts: qcom: sa8775p: Mark APPS and PCIe SMMUs as DMA coherent commit: 421688265d7f5d3ff4211982e7231765378bb64f Best regards,
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 23f1b2e5e624..95691ab58a23 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -3070,6 +3070,7 @@ reg = <0x0 0x15000000 0x0 0x100000>; #iommu-cells = <2>; #global-interrupts = <2>; + dma-coherent; interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, @@ -3208,6 +3209,7 @@ reg = <0x0 0x15200000 0x0 0x80000>; #iommu-cells = <2>; #global-interrupts = <2>; + dma-coherent; interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>,