| Message ID | 20240731062916.2680823-4-quic_skakitap@quicinc.com (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | Add camera clock controller support for SM8150 | expand |
On Wed, Jul 31, 2024 at 11:59:11AM GMT, Satya Priya Kakitapalli wrote: > Currently, clk_zonda_pll_set_rate polls for the PLL to lock even if the > PLL is disabled. However, if the PLL is disabled then LOCK_DET will > never assert and we'll return an error. There is no reason to poll > LOCK_DET if the PLL is already disabled, so skip polling in this case. > > Fixes: f21b6bfecc27 ("clk: qcom: clk-alpha-pll: add support for zonda pll") > Cc: stable@vger.kernel.org > Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> > --- > drivers/clk/qcom/clk-alpha-pll.c | 3 +++ > 1 file changed, 3 insertions(+) > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index eb5626095916..2ebeb277cb4d 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -2136,6 +2136,9 @@ static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate, regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); + if (!clk_hw_is_enabled(hw)) + return 0; + /* Wait before polling for the frequency latch */ udelay(5);
Currently, clk_zonda_pll_set_rate polls for the PLL to lock even if the PLL is disabled. However, if the PLL is disabled then LOCK_DET will never assert and we'll return an error. There is no reason to poll LOCK_DET if the PLL is already disabled, so skip polling in this case. Fixes: f21b6bfecc27 ("clk: qcom: clk-alpha-pll: add support for zonda pll") Cc: stable@vger.kernel.org Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> --- drivers/clk/qcom/clk-alpha-pll.c | 3 +++ 1 file changed, 3 insertions(+)