diff mbox series

[v2] phy: qcom: qmp: Add debug prints for register writes

Message ID 20240731115637.90351-1-manivannan.sadhasivam@linaro.org
State Superseded
Headers show
Series [v2] phy: qcom: qmp: Add debug prints for register writes | expand

Commit Message

Manivannan Sadhasivam July 31, 2024, 11:56 a.m. UTC
These register prints are useful to validate the init sequence against the
Qcom internal documentation and also to share with the Qcom hw engineers to
debug issues related to PHY.

Sample debug prints:

QMP PHY: Writing Reg: QSERDES_V5_COM_SYSCLK_EN_SEL Offset: 0x0094 Val: 0xd9
QMP PHY: Writing Reg: QSERDES_V5_COM_HSCLK_SEL Offset: 0x0158 Val: 0x11

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---

Changes in v2:

* Modifed the debug print to include reg offset

 drivers/phy/qualcomm/phy-qcom-qmp-common.h | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Bjorn Andersson Aug. 1, 2024, 2:26 a.m. UTC | #1
On Wed, Jul 31, 2024 at 05:26:37PM GMT, Manivannan Sadhasivam wrote:
> These register prints are useful to validate the init sequence against the
> Qcom internal documentation and also to share with the Qcom hw engineers to
> debug issues related to PHY.
> 

I've written this patch every time I've touched one of these PHYs, so I
certainly like this.

> Sample debug prints:
> 
> QMP PHY: Writing Reg: QSERDES_V5_COM_SYSCLK_EN_SEL Offset: 0x0094 Val: 0xd9
> QMP PHY: Writing Reg: QSERDES_V5_COM_HSCLK_SEL Offset: 0x0158 Val: 0x11

That said, with multiple instances of PHYs being configured at about the
same time it seems this would benefit greatly from something identifying
which PHY instance the write relates to?

dev_dbg() would certainly be nice...

> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> 
> Changes in v2:
> 
> * Modifed the debug print to include reg offset
> 
>  drivers/phy/qualcomm/phy-qcom-qmp-common.h | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-common.h b/drivers/phy/qualcomm/phy-qcom-qmp-common.h
> index 799384210509..40beb413328f 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-common.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-common.h
> @@ -9,6 +9,7 @@
>  struct qmp_phy_init_tbl {
>  	unsigned int offset;
>  	unsigned int val;
> +	char *name;

const?

Regards,
Bjorn

>  	/*
>  	 * mask of lanes for which this register is written
>  	 * for cases when second lane needs different values
> @@ -20,6 +21,7 @@ struct qmp_phy_init_tbl {
>  	{				\
>  		.offset = o,		\
>  		.val = v,		\
> +		.name = #o,		\
>  		.lane_mask = 0xff,	\
>  	}
>  
> @@ -27,6 +29,7 @@ struct qmp_phy_init_tbl {
>  	{				\
>  		.offset = o,		\
>  		.val = v,		\
> +		.name = #o,		\
>  		.lane_mask = l,		\
>  	}
>  
> @@ -45,6 +48,8 @@ static inline void qmp_configure_lane(void __iomem *base,
>  		if (!(t->lane_mask & lane_mask))
>  			continue;
>  
> +		pr_debug("QMP PHY: Writing Reg: %s Offset: 0x%04x Val: 0x%02x\n",
> +			t->name, t->offset, t->val);
>  		writel(t->val, base + t->offset);
>  	}
>  }
> -- 
> 2.25.1
> 
>
Manivannan Sadhasivam Aug. 1, 2024, 6:58 a.m. UTC | #2
On Wed, Jul 31, 2024 at 09:26:27PM -0500, Bjorn Andersson wrote:
> On Wed, Jul 31, 2024 at 05:26:37PM GMT, Manivannan Sadhasivam wrote:
> > These register prints are useful to validate the init sequence against the
> > Qcom internal documentation and also to share with the Qcom hw engineers to
> > debug issues related to PHY.
> > 
> 
> I've written this patch every time I've touched one of these PHYs, so I
> certainly like this.
> 

Me too :) I've been carrying this as an out-of-tree patch ever since I started
bringing up Qcom chipsets.

> > Sample debug prints:
> > 
> > QMP PHY: Writing Reg: QSERDES_V5_COM_SYSCLK_EN_SEL Offset: 0x0094 Val: 0xd9
> > QMP PHY: Writing Reg: QSERDES_V5_COM_HSCLK_SEL Offset: 0x0158 Val: 0x11
> 
> That said, with multiple instances of PHYs being configured at about the
> same time it seems this would benefit greatly from something identifying
> which PHY instance the write relates to?
> 
> dev_dbg() would certainly be nice...
> 

I understood that after comments from Dmitry. So v4 has this:

qcom-qmp-pcie-phy 1c0e000.phy: Writing Reg: QSERDES_V5_COM_SYSCLK_EN_SEL Offset: 0x0094 Val: 0xd9

- Mani

> > 
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > ---
> > 
> > Changes in v2:
> > 
> > * Modifed the debug print to include reg offset
> > 
> >  drivers/phy/qualcomm/phy-qcom-qmp-common.h | 5 +++++
> >  1 file changed, 5 insertions(+)
> > 
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-common.h b/drivers/phy/qualcomm/phy-qcom-qmp-common.h
> > index 799384210509..40beb413328f 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-common.h
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-common.h
> > @@ -9,6 +9,7 @@
> >  struct qmp_phy_init_tbl {
> >  	unsigned int offset;
> >  	unsigned int val;
> > +	char *name;
> 
> const?
> 
> Regards,
> Bjorn
> 
> >  	/*
> >  	 * mask of lanes for which this register is written
> >  	 * for cases when second lane needs different values
> > @@ -20,6 +21,7 @@ struct qmp_phy_init_tbl {
> >  	{				\
> >  		.offset = o,		\
> >  		.val = v,		\
> > +		.name = #o,		\
> >  		.lane_mask = 0xff,	\
> >  	}
> >  
> > @@ -27,6 +29,7 @@ struct qmp_phy_init_tbl {
> >  	{				\
> >  		.offset = o,		\
> >  		.val = v,		\
> > +		.name = #o,		\
> >  		.lane_mask = l,		\
> >  	}
> >  
> > @@ -45,6 +48,8 @@ static inline void qmp_configure_lane(void __iomem *base,
> >  		if (!(t->lane_mask & lane_mask))
> >  			continue;
> >  
> > +		pr_debug("QMP PHY: Writing Reg: %s Offset: 0x%04x Val: 0x%02x\n",
> > +			t->name, t->offset, t->val);
> >  		writel(t->val, base + t->offset);
> >  	}
> >  }
> > -- 
> > 2.25.1
> > 
> >
diff mbox series

Patch

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-common.h b/drivers/phy/qualcomm/phy-qcom-qmp-common.h
index 799384210509..40beb413328f 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-common.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-common.h
@@ -9,6 +9,7 @@ 
 struct qmp_phy_init_tbl {
 	unsigned int offset;
 	unsigned int val;
+	char *name;
 	/*
 	 * mask of lanes for which this register is written
 	 * for cases when second lane needs different values
@@ -20,6 +21,7 @@  struct qmp_phy_init_tbl {
 	{				\
 		.offset = o,		\
 		.val = v,		\
+		.name = #o,		\
 		.lane_mask = 0xff,	\
 	}
 
@@ -27,6 +29,7 @@  struct qmp_phy_init_tbl {
 	{				\
 		.offset = o,		\
 		.val = v,		\
+		.name = #o,		\
 		.lane_mask = l,		\
 	}
 
@@ -45,6 +48,8 @@  static inline void qmp_configure_lane(void __iomem *base,
 		if (!(t->lane_mask & lane_mask))
 			continue;
 
+		pr_debug("QMP PHY: Writing Reg: %s Offset: 0x%04x Val: 0x%02x\n",
+			t->name, t->offset, t->val);
 		writel(t->val, base + t->offset);
 	}
 }