| Message ID | 20240730073123.72992-1-marco@palumbi.it (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | hw/arm/mps2-tz.c: fix RX/TX interrupts order | expand |
On Tue, 30 Jul 2024 at 08:32, <marco@palumbi.it> wrote: > > From: Marco Palumbi <Marco.Palumbi@tii.ae> > > The order of the RX and TX interrupts are swapped. > This commit fixes the order as per the following documents: > * https://developer.arm.com/documentation/dai0505/latest/ > * https://developer.arm.com/documentation/dai0521/latest/ > * https://developer.arm.com/documentation/dai0524/latest/ > * https://developer.arm.com/documentation/dai0547/latest/ > > Signed-off-by: Marco Palumbi <Marco.Palumbi@tii.ae> Thanks for this patch, I've applied it to my target-arm.next queue. I checked the other boards that use the cmsdk UART, and they all get the tx/rx interrupt order right, so this is the only place that needed fixing. I suspect that the guest images I tested didn't care about the separate tx/rx interrupts and only used the combined irq. thanks -- PMM
Thanks Peter for your time! Marco Palumbi Senior Cryptography Engineer PO Box: 9639 Masdar City, Abu Dhabi, UAE M: +39 349 786 0737 E: marco.palumbi@tii.ae tii.ae This email and any files transmitted with it are strictly confidential and intended solely for the use of the individual or entity to whom they are addressed. If you have received this email in error please notify the sender. This message contains confidential information and is intended only for the individual named. If you are not the named addressee you should not disseminate, distribute or copy this e-mail. Please notify the sender immediately by e-mail if you have received this e-mail by mistake and delete this e-mail from your system. If you are not the intended recipient you are notified that disclosing, copying, distributing or taking any action in reliance on the contents of this information is strictly prohibited. -----Original Message----- From: Peter Maydell <peter.maydell@linaro.org> Sent: Wednesday, July 31, 2024 1:38 PM To: marco@palumbi.it Cc: qemu-devel@nongnu.org; Marco Palumbi <Marco.Palumbi@tii.ae>; qemu-arm@nongnu.org; qemu-stable@nongnu.org; qemu-trivial@nongnu.org Subject: Re: [PATCH] hw/arm/mps2-tz.c: fix RX/TX interrupts order On Tue, 30 Jul 2024 at 08:32, <marco@palumbi.it> wrote: > > From: Marco Palumbi <Marco.Palumbi@tii.ae> > > The order of the RX and TX interrupts are swapped. > This commit fixes the order as per the following documents: > * > https://are01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fprot > ect.checkpoint.com%2Fv2%2F___https%3A%2F%2Fdeveloper.arm.com%2Fdocumen > tation%2Fdai0505%2Flatest%2F___.bWVjMTp0ZWNobm9sb2d5aW5ub3ZhdGlvbmluc3 > RpdHV0ZTpjOm86YTlkNGRjMjcxZTBmMWJjNjlmMzc2NGE0OWY4ZmU5MWY6Njo0MzVhOjY3 > NjVkOGIwNWJkMzgwMGJkMzdlMWJmYmE5MmFhY2E2MzhhOTQyZjQ4ZDA5MmI0ODg2NTc1Yj > QxYzM1MzY4N2Q6cDpUOk4&data=05%7C02%7CMarco.Palumbi%40tii.ae%7C063b7e0f > d4634265eb5808dcb155575b%7Cf0869253be004a379c7737742cb15c38%7C1%7C0%7C > 638580227306410621%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjo > iV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C0%7C%7C%7C&sdata=nW%2F6AR%2F > E2tlpQ%2FSNSvDJyQf71YIbk83KVcZzGnmP5Lk%3D&reserved=0 > * > https://are01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fprot > ect.checkpoint.com%2Fv2%2F___https%3A%2F%2Fdeveloper.arm.com%2Fdocumen > tation%2Fdai0521%2Flatest%2F___.bWVjMTp0ZWNobm9sb2d5aW5ub3ZhdGlvbmluc3 > RpdHV0ZTpjOm86YTlkNGRjMjcxZTBmMWJjNjlmMzc2NGE0OWY4ZmU5MWY6NjoxM2NkOjY4 > YTI5ZTFmNDU4YTg3NTQxZGJmMzE1ZjQ4MWU3MTk1ZWRiMWRiOTdmNTIwMWU1OGYyNThkZm > U4MzkzNWZkY2Y6cDpUOk4&data=05%7C02%7CMarco.Palumbi%40tii.ae%7C063b7e0f > d4634265eb5808dcb155575b%7Cf0869253be004a379c7737742cb15c38%7C1%7C0%7C > 638580227306419690%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjo > iV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C0%7C%7C%7C&sdata=YGw4NsxbW01 > i46Gm%2BgBzQIOB6nOqL16P3Deblg3OcRw%3D&reserved=0 > * > https://are01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fprot > ect.checkpoint.com%2Fv2%2F___https%3A%2F%2Fdeveloper.arm.com%2Fdocumen > tation%2Fdai0524%2Flatest%2F___.bWVjMTp0ZWNobm9sb2d5aW5ub3ZhdGlvbmluc3 > RpdHV0ZTpjOm86YTlkNGRjMjcxZTBmMWJjNjlmMzc2NGE0OWY4ZmU5MWY6Njo3N2NjOmQx > YmIyN2YxY2Q3YWJjMTBhM2I1Zjk1NGM4NTBjZDlhNTVhYjA2NDMwZDQwOTUzZjNkZmU4ZG > NjYmNkMmUxMTI6cDpUOk4&data=05%7C02%7CMarco.Palumbi%40tii.ae%7C063b7e0f > d4634265eb5808dcb155575b%7Cf0869253be004a379c7737742cb15c38%7C1%7C0%7C > 638580227306425926%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjo > iV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C0%7C%7C%7C&sdata=0poH91SU6NE > f4%2BD3%2BqH5WNDgTXXfZ4PA7buG0bwKQlE%3D&reserved=0 > * > https://are01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fprot > ect.checkpoint.com%2Fv2%2F___https%3A%2F%2Fdeveloper.arm.com%2Fdocumen > tation%2Fdai0547%2Flatest%2F___.bWVjMTp0ZWNobm9sb2d5aW5ub3ZhdGlvbmluc3 > RpdHV0ZTpjOm86YTlkNGRjMjcxZTBmMWJjNjlmMzc2NGE0OWY4ZmU5MWY6NjplOTcyOmUy > MzEyNTdlYzlmOTRjOWY5NjY4YmExZDc3NGQ5NWNhYmY2NmEzNjI2ZGMwYjI3ZWZlZTU2YW > UyZjQ1NDFhMTI6cDpUOk4&data=05%7C02%7CMarco.Palumbi%40tii.ae%7C063b7e0f > d4634265eb5808dcb155575b%7Cf0869253be004a379c7737742cb15c38%7C1%7C0%7C > 638580227306430786%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjo > iV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C0%7C%7C%7C&sdata=LWgkq6rb9vQ > 0q4VhuPmflWyFLCtMTjg6DWe3j9h381w%3D&reserved=0 > > Signed-off-by: Marco Palumbi <Marco.Palumbi@tii.ae> Thanks for this patch, I've applied it to my target-arm.next queue. I checked the other boards that use the cmsdk UART, and they all get the tx/rx interrupt order right, so this is the only place that needed fixing. I suspect that the guest images I tested didn't care about the separate tx/rx interrupts and only used the combined irq. thanks -- PMM
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index a2d18afd79..aec57c0d68 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -435,7 +435,7 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, const int *irqs, const PPCExtraData *extradata) { - /* The irq[] array is tx, rx, combined, in that order */ + /* The irq[] array is rx, tx, combined, in that order */ MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); CMSDKAPBUART *uart = opaque; int i = uart - &mms->uart[0]; @@ -447,8 +447,8 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->apb_periph_frq); sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal); s = SYS_BUS_DEVICE(uart); - sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); - sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1])); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[1])); + sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[0])); sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); sysbus_connect_irq(s, 4, get_sse_irq_in(mms, irqs[2]));