| Message ID | 20240729175327.73705-6-debug@rivosinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv support for control flow integrity extensions | expand |
On 7/30/24 03:53, Deepak Gupta wrote: > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index acba90f170..c746d7df08 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -20,6 +20,7 @@ > #include "qemu/log.h" > #include "cpu.h" > #include "tcg/tcg-op.h" > +#include "tcg/tcg-temp-internal.h" No, this is internal to tcg, as the filename says. > #include "exec/exec-all.h" > #include "exec/helper-proto.h" > #include "exec/helper-gen.h" > @@ -44,6 +45,7 @@ static TCGv load_val; > /* globals for PM CSRs */ > static TCGv pm_mask; > static TCGv pm_base; > +static TCGOp *cfi_lp_check; > > /* > * If an operation is being performed on less than TARGET_LONG_BITS, > @@ -116,6 +118,9 @@ typedef struct DisasContext { > bool frm_valid; > bool insn_start_updated; > const GPtrArray *decoders; > + /* zicfilp extension. cfi enabled or not. lp expected or not */ > + bool fcfi_enabled; > + bool fcfi_lp_expected; > } DisasContext; > > static inline bool has_ext(DisasContext *ctx, uint32_t ext) > @@ -1238,6 +1243,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) > ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); > ctx->ztso = cpu->cfg.ext_ztso; > ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); > + ctx->fcfi_lp_expected = FIELD_EX32(tb_flags, TB_FLAGS, FCFI_LP_EXPECTED); > + ctx->fcfi_enabled = cpu_get_fcfien(env) && ctx->fcfi_lp_expected; This is incorrect. You cannot check fcfien like this here; you must place it in a tb flag like "lp_expected". > @@ -1245,6 +1252,39 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) > > static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) > { > + DisasContext *ctx = container_of(db, DisasContext, base); > + > + if (ctx->fcfi_lp_expected) { > + /* > + * Since we can't look ahead to confirm that the first > + * instruction is a legal landing pad instruction, emit > + * compare-and-branch sequence that will be fixed-up in > + * riscv_tr_tb_stop() to either statically hit or skip an > + * illegal instruction exception depending on whether the > + * flag was lowered by translation of a CJLP or JLP as > + * the first instruction in the block. > + */ > + TCGv_i32 immediate; > + TCGLabel *l; > + l = gen_new_label(); > + immediate = tcg_temp_new_i32(); > + tcg_gen_movi_i32(immediate, 0); > + cfi_lp_check = tcg_last_op(); > + tcg_gen_brcondi_i32(TCG_COND_EQ, immediate, 0, l); > + tcg_temp_free_i32(immediate); > + tcg_gen_st_tl( > + tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL), > + tcg_env, offsetof(CPURISCVState, sw_check_code)); > + generate_exception(ctx, RISCV_EXCP_SW_CHECK); > + gen_set_label(l); > + /* > + * Despite the use of gen_exception_illegal(), the rest of > + * the TB needs to be generated. The TCG optimizer will > + * clean things up depending on which path ends up being > + * active. > + */ > + ctx->base.is_jmp = DISAS_NEXT; > + } > } Better to simply delay the check to the first insn load. See aarch64_tr_translate_insn, dc_isar_feature(aa64_bti, s). r~
On Mon, Jul 29, 2024 at 7:34 PM Richard Henderson <richard.henderson@linaro.org> wrote: > > On 7/30/24 03:53, Deepak Gupta wrote: > > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > > index acba90f170..c746d7df08 100644 > > --- a/target/riscv/translate.c > > +++ b/target/riscv/translate.c > > @@ -20,6 +20,7 @@ > > #include "qemu/log.h" > > #include "cpu.h" > > #include "tcg/tcg-op.h" > > +#include "tcg/tcg-temp-internal.h" > > No, this is internal to tcg, as the filename says. Ok > > > > #include "exec/exec-all.h" > > #include "exec/helper-proto.h" > > #include "exec/helper-gen.h" > > @@ -44,6 +45,7 @@ static TCGv load_val; > > /* globals for PM CSRs */ > > static TCGv pm_mask; > > static TCGv pm_base; > > +static TCGOp *cfi_lp_check; > > > > /* > > * If an operation is being performed on less than TARGET_LONG_BITS, > > @@ -116,6 +118,9 @@ typedef struct DisasContext { > > bool frm_valid; > > bool insn_start_updated; > > const GPtrArray *decoders; > > + /* zicfilp extension. cfi enabled or not. lp expected or not */ > > + bool fcfi_enabled; > > + bool fcfi_lp_expected; > > } DisasContext; > > > > static inline bool has_ext(DisasContext *ctx, uint32_t ext) > > @@ -1238,6 +1243,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) > > ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); > > ctx->ztso = cpu->cfg.ext_ztso; > > ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); > > + ctx->fcfi_lp_expected = FIELD_EX32(tb_flags, TB_FLAGS, FCFI_LP_EXPECTED); > > + ctx->fcfi_enabled = cpu_get_fcfien(env) && ctx->fcfi_lp_expected; > > This is incorrect. You cannot check fcfien like this here; you must place it in a tb flag > like "lp_expected". hmm... you've suggested below to use `aarch64_tr_translate_insn` and check if it's the first instruction. and put the check there. In that case I won't need FCFI_LP_EXPECTED TB flag. Then I would rather use it as FCFI_ENABLED TB flag. > > > > @@ -1245,6 +1252,39 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) > > > > static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) > > { > > + DisasContext *ctx = container_of(db, DisasContext, base); > > + > > + if (ctx->fcfi_lp_expected) { > > + /* > > + * Since we can't look ahead to confirm that the first > > + * instruction is a legal landing pad instruction, emit > > + * compare-and-branch sequence that will be fixed-up in > > + * riscv_tr_tb_stop() to either statically hit or skip an > > + * illegal instruction exception depending on whether the > > + * flag was lowered by translation of a CJLP or JLP as > > + * the first instruction in the block. > > + */ > > + TCGv_i32 immediate; > > + TCGLabel *l; > > + l = gen_new_label(); > > + immediate = tcg_temp_new_i32(); > > + tcg_gen_movi_i32(immediate, 0); > > + cfi_lp_check = tcg_last_op(); > > + tcg_gen_brcondi_i32(TCG_COND_EQ, immediate, 0, l); > > + tcg_temp_free_i32(immediate); > > + tcg_gen_st_tl( > > + tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL), > > + tcg_env, offsetof(CPURISCVState, sw_check_code)); > > + generate_exception(ctx, RISCV_EXCP_SW_CHECK); > > + gen_set_label(l); > > + /* > > + * Despite the use of gen_exception_illegal(), the rest of > > + * the TB needs to be generated. The TCG optimizer will > > + * clean things up depending on which path ends up being > > + * active. > > + */ > > + ctx->base.is_jmp = DISAS_NEXT; > > + } > > } > > Better to simply delay the check to the first insn load. > See aarch64_tr_translate_insn, dc_isar_feature(aa64_bti, s). Hmmm... Thanks, I think it'll probably make it simpler. Let me re-work this logic and test it out if it works. > > > r~ >
On 8/1/24 16:59, Deepak Gupta wrote: > hmm... you've suggested below to use `aarch64_tr_translate_insn` and > check if it's the first instruction. > and put the check there. > In that case I won't need FCFI_LP_EXPECTED TB flag. > Then I would rather use it as FCFI_ENABLED TB flag. You will need both bits. r~
On Thu, Aug 1, 2024 at 2:12 AM Richard Henderson <richard.henderson@linaro.org> wrote: > > On 8/1/24 16:59, Deepak Gupta wrote: > > hmm... you've suggested below to use `aarch64_tr_translate_insn` and > > check if it's the first instruction. > > and put the check there. > > In that case I won't need FCFI_LP_EXPECTED TB flag. > > Then I would rather use it as FCFI_ENABLED TB flag. > > You will need both bits. I was thinking of following logic and wanted to run by you to check if I am missing something obvious. ---Recording fcfi_enabled in disascontext--- Add a FCFI_ENABLED TB flag which gets set (or not set) in `cpu_get_tb_cpu_state` And `riscv_tr_init_disas_context` does DisasContext->fcfi_enabled = extracts FCFI_ENABLED TB flag. ---Set elp on translation of indirect jump/call---- translation for jalr (instruction which triggers elp state) does following trans_jalr: if (DisasContext->fcfi_enabled) env->elp = LP_EXPECTED ---Check if first instruction is not a landing pad---- In `riscv_tr_translate_insn` if (first instruction of TB && env->elp) { if (`insn` is not a `lpad` (landing pad) encoding) raise_exception(); } ---label check embedded in landing pad instruction--- In `trans_lpad` env->elp = NO_LP_EXPECTED invoke a helper which will check embedded label value against value in ISA defined register (x7) I think this will work with just one TB flag (FCFI_ENABLED). Let me know if I am missing something. > > > r~
On 8/2/24 03:05, Deepak Gupta wrote: > On Thu, Aug 1, 2024 at 2:12 AM Richard Henderson > <richard.henderson@linaro.org> wrote: >> >> On 8/1/24 16:59, Deepak Gupta wrote: >>> hmm... you've suggested below to use `aarch64_tr_translate_insn` and >>> check if it's the first instruction. >>> and put the check there. >>> In that case I won't need FCFI_LP_EXPECTED TB flag. >>> Then I would rather use it as FCFI_ENABLED TB flag. >> >> You will need both bits. > > I was thinking of following logic and wanted to run by you to check if > I am missing something > obvious. > > ---Recording fcfi_enabled in disascontext--- > Add a FCFI_ENABLED TB flag which gets set (or not set) in `cpu_get_tb_cpu_state` > > And `riscv_tr_init_disas_context` does > DisasContext->fcfi_enabled = extracts FCFI_ENABLED TB flag. > > > ---Set elp on translation of indirect jump/call---- > translation for jalr (instruction which triggers elp state) does following > > trans_jalr: > if (DisasContext->fcfi_enabled) > env->elp = LP_EXPECTED > > ---Check if first instruction is not a landing pad---- > In `riscv_tr_translate_insn` > > if (first instruction of TB && env->elp) { You can't access env->elp during translation like this. That's why you need either (1) the LP_EXPECTED bit in tb_flags as well, or (2) a runtime test against elp. > if (`insn` is not a `lpad` (landing pad) encoding) > raise_exception(); > } > > ---label check embedded in landing pad instruction--- > In `trans_lpad` > > env->elp = NO_LP_EXPECTED > invoke a helper which will check embedded label value against value in > ISA defined register (x7) You don't need a helper for such a trivial operation. tcg_gen_extract_tl(tmp, get_gpr(ctx, 7, EXT_NONE), 12, 20); tcg_gen_brcondi_tl(TCG_COND_EQ, tmp, a->imm, skip); generate_exception(...); r~
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 12334f9540..7fed5d2750 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -606,6 +606,8 @@ FIELD(TB_FLAGS, ITRIGGER, 22, 1) FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) FIELD(TB_FLAGS, PRIV, 24, 2) FIELD(TB_FLAGS, AXL, 26, 2) +/* zicfilp needs a TB flag to track indirect branches */ +FIELD(TB_FLAGS, FCFI_LP_EXPECTED, 28, 1) #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 127f2179dc..477e24feaf 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -691,6 +691,9 @@ typedef enum RISCVException { RISCV_EXCP_SEMIHOST = 0x3f, } RISCVException; +/* zicfilp defines lp violation results in sw check with tval = 2*/ +#define RISCV_EXCP_SW_CHECK_FCFI_TVAL 2 + #define RISCV_EXCP_INT_FLAG 0x80000000 #define RISCV_EXCP_INT_MASK 0x7fffffff diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 41bc73ad60..2cb1d45467 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -134,6 +134,18 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); } + if (cpu_get_fcfien(env)) { + /* + * For Forward CFI, only the expectation of a lpcll at + * the start of the block is tracked (which can only happen + * when FCFI is enabled for the current processor mode). A jump + * or call at the end of the previous TB will have updated + * env->elp to indicate the expectation. + */ + flags = FIELD_DP32(flags, TB_FLAGS, FCFI_LP_EXPECTED, + env->elp != NO_LP_EXPECTED); + } + #ifdef CONFIG_USER_ONLY fs = EXT_STATUS_DIRTY; vs = EXT_STATUS_DIRTY; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index acba90f170..c746d7df08 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -20,6 +20,7 @@ #include "qemu/log.h" #include "cpu.h" #include "tcg/tcg-op.h" +#include "tcg/tcg-temp-internal.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -44,6 +45,7 @@ static TCGv load_val; /* globals for PM CSRs */ static TCGv pm_mask; static TCGv pm_base; +static TCGOp *cfi_lp_check; /* * If an operation is being performed on less than TARGET_LONG_BITS, @@ -116,6 +118,9 @@ typedef struct DisasContext { bool frm_valid; bool insn_start_updated; const GPtrArray *decoders; + /* zicfilp extension. cfi enabled or not. lp expected or not */ + bool fcfi_enabled; + bool fcfi_lp_expected; } DisasContext; static inline bool has_ext(DisasContext *ctx, uint32_t ext) @@ -1238,6 +1243,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); ctx->ztso = cpu->cfg.ext_ztso; ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); + ctx->fcfi_lp_expected = FIELD_EX32(tb_flags, TB_FLAGS, FCFI_LP_EXPECTED); + ctx->fcfi_enabled = cpu_get_fcfien(env) && ctx->fcfi_lp_expected; ctx->zero = tcg_constant_tl(0); ctx->virt_inst_excp = false; ctx->decoders = cpu->decoders; @@ -1245,6 +1252,39 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) { + DisasContext *ctx = container_of(db, DisasContext, base); + + if (ctx->fcfi_lp_expected) { + /* + * Since we can't look ahead to confirm that the first + * instruction is a legal landing pad instruction, emit + * compare-and-branch sequence that will be fixed-up in + * riscv_tr_tb_stop() to either statically hit or skip an + * illegal instruction exception depending on whether the + * flag was lowered by translation of a CJLP or JLP as + * the first instruction in the block. + */ + TCGv_i32 immediate; + TCGLabel *l; + l = gen_new_label(); + immediate = tcg_temp_new_i32(); + tcg_gen_movi_i32(immediate, 0); + cfi_lp_check = tcg_last_op(); + tcg_gen_brcondi_i32(TCG_COND_EQ, immediate, 0, l); + tcg_temp_free_i32(immediate); + tcg_gen_st_tl( + tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL), + tcg_env, offsetof(CPURISCVState, sw_check_code)); + generate_exception(ctx, RISCV_EXCP_SW_CHECK); + gen_set_label(l); + /* + * Despite the use of gen_exception_illegal(), the rest of + * the TB needs to be generated. The TCG optimizer will + * clean things up depending on which path ends up being + * active. + */ + ctx->base.is_jmp = DISAS_NEXT; + } } static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) @@ -1303,6 +1343,14 @@ static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) default: g_assert_not_reached(); } + + if (ctx->fcfi_lp_expected) { + /* + * If the "lp expected" flag is still up, the block needs to take an + * illegal instruction exception. + */ + tcg_set_insn_param(cfi_lp_check, 1, tcgv_i32_arg(tcg_constant_i32(1))); + } } static const TranslatorOps riscv_tr_ops = {
zicfilp protects forward control flow (if enabled) by enforcing all indirect call and jmp must land on a landing pad instruction `lpad`. If target of an indirect call or jmp is not `lpad` then cpu/hart must raise a sw check exception with tval = 2. This patch implements the mechanism using TCG. Target architecture branch instruction must define the end of a TB. Using this property, during translation of branch instruction, TB flag = FCFI_LP_EXPECTED can be set. Translation of target TB can check if FCFI_LP_EXPECTED flag is set and a flag (fcfi_lp_expected) can be set in DisasContext. If `lpad` gets translated, fcfi_lp_expected flag in DisasContext can be cleared. Else it'll fault. This patch also also adds flag for forward cfi in DisasContext. Signed-off-by: Deepak Gupta <debug@rivosinc.com> Co-developed-by: Jim Shu <jim.shu@sifive.com> Co-developed-by: Andy Chiu <andy.chiu@sifive.com> --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_helper.c | 12 ++++++++++ target/riscv/translate.c | 48 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 65 insertions(+)