diff mbox series

[02/18] bsd-user: Add RISC-V CPU execution loop and syscall handling

Message ID 20240802083423.142365-3-itachis@FreeBSD.org (mailing list archive)
State New, archived
Headers show
Series bsd-user: Comprehensive RISCV support | expand

Commit Message

Ajeet Singh Aug. 2, 2024, 8:34 a.m. UTC 
From: Mark Corbin <mark.corbin@embecsom.com>

Implemented the RISC-V CPU execution loop, including handling various
exceptions and system calls. The loop continuously executes CPU
instructions,processes exceptions, and handles system calls by invoking
FreeBSD syscall handlers.

Signed-off-by: Mark Corbin <mark.corbin@embecsom.com>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
Co-authored-by: Kyle Evans <kevans@FreeBSD.org>
---
 bsd-user/riscv/target_arch_cpu.h | 94 ++++++++++++++++++++++++++++++++
 1 file changed, 94 insertions(+)

Comments

Richard Henderson Aug. 2, 2024, 12:54 p.m. UTC | #1 
On 8/2/24 18:34, Ajeet Singh wrote:
> From: Mark Corbin<mark.corbin@embecsom.com>
> 
> Implemented the RISC-V CPU execution loop, including handling various
> exceptions and system calls. The loop continuously executes CPU
> instructions,processes exceptions, and handles system calls by invoking
> FreeBSD syscall handlers.
> 
> Signed-off-by: Mark Corbin<mark.corbin@embecsom.com>
> Signed-off-by: Ajeet Singh<itachis@FreeBSD.org>
> Co-authored-by: Jessica Clarke<jrtc27@jrtc27.com>
> Co-authored-by: Kyle Evans<kevans@FreeBSD.org>
> ---
>   bsd-user/riscv/target_arch_cpu.h | 94 ++++++++++++++++++++++++++++++++
>   1 file changed, 94 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
diff mbox series

Patch

diff --git a/bsd-user/riscv/target_arch_cpu.h b/bsd-user/riscv/target_arch_cpu.h
index 28f56560e0..5b436b2ac9 100644
--- a/bsd-user/riscv/target_arch_cpu.h
+++ b/bsd-user/riscv/target_arch_cpu.h
@@ -36,4 +36,98 @@  static inline void target_cpu_init(CPURISCVState *env,
     env->pc = regs->sepc;
 }
 
+static inline void target_cpu_loop(CPURISCVState *env)
+{
+    CPUState *cs = env_cpu(env);
+    int trapnr;
+    abi_long ret;
+    unsigned int syscall_num;
+    int32_t signo, code;
+
+    for (;;) {
+        cpu_exec_start(cs);
+        trapnr = cpu_exec(cs);
+        cpu_exec_end(cs);
+        process_queued_cpu_work(cs);
+
+        signo = 0;
+
+        switch (trapnr) {
+        case EXCP_INTERRUPT:
+            /* just indicate that signals should be handled asap */
+            break;
+        case EXCP_ATOMIC:
+            cpu_exec_step_atomic(cs);
+            break;
+        case RISCV_EXCP_U_ECALL:
+            syscall_num = env->gpr[xT0]; /* t0 */
+            env->pc += TARGET_INSN_SIZE;
+            /* Compare to cpu_fetch_syscall_args() in riscv/riscv/trap.c */
+            if (TARGET_FREEBSD_NR___syscall == syscall_num ||
+                TARGET_FREEBSD_NR_syscall == syscall_num) {
+                ret = do_freebsd_syscall(env,
+                                         env->gpr[xA0], /* a0 */
+                                         env->gpr[xA1], /* a1 */
+                                         env->gpr[xA2], /* a2 */
+                                         env->gpr[xA3], /* a3 */
+                                         env->gpr[xA4], /* a4 */
+                                         env->gpr[xA5], /* a5 */
+                                         env->gpr[xA6], /* a6 */
+                                         env->gpr[xA7], /* a7 */
+                                         0);
+            } else {
+                ret = do_freebsd_syscall(env,
+                                         syscall_num,
+                                         env->gpr[xA0], /* a0 */
+                                         env->gpr[xA1], /* a1 */
+                                         env->gpr[xA2], /* a2 */
+                                         env->gpr[xA3], /* a3 */
+                                         env->gpr[xA4], /* a4 */
+                                         env->gpr[xA5], /* a5 */
+                                         env->gpr[xA6], /* a6 */
+                                         env->gpr[xA7]  /* a7 */
+                    );
+            }
+
+            /*
+             * Compare to cpu_set_syscall_retval() in
+             * riscv/riscv/vm_machdep.c
+             */
+            if (ret >= 0) {
+                env->gpr[xA0] = ret; /* a0 */
+                env->gpr[xT0] = 0;   /* t0 */
+            } else if (ret == -TARGET_ERESTART) {
+                env->pc -= TARGET_INSN_SIZE;
+            } else if (ret != -TARGET_EJUSTRETURN) {
+                env->gpr[xA0] = -ret; /* a0 */
+                env->gpr[xT0] = 1;   /* t0 */
+            }
+            break;
+        case RISCV_EXCP_ILLEGAL_INST:
+            signo = TARGET_SIGILL;
+            code = TARGET_ILL_ILLOPC;
+            break;
+        case RISCV_EXCP_BREAKPOINT:
+            signo = TARGET_SIGTRAP;
+            code = TARGET_TRAP_BRKPT;
+            break;
+        case EXCP_DEBUG:
+            signo = TARGET_SIGTRAP;
+            code = TARGET_TRAP_BRKPT;
+            break;
+        default:
+            fprintf(stderr, "qemu: unhandled CPU exception "
+                "0x%x - aborting\n", trapnr);
+            cpu_dump_state(cs, stderr, 0);
+            abort();
+        }
+
+        if (signo) {
+            force_sig_fault(signo, code, env->pc);
+        }
+
+        process_pending_signals(env);
+    }
+}
+
 #endif /* TARGET_ARCH_CPU_H */