| Message ID | 20240802083423.142365-7-itachis@FreeBSD.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | bsd-user: Comprehensive RISCV support | expand |
On 8/2/24 18:34, Ajeet Singh wrote: > From: Mark Corbin <mark.corbin@embecsom.com> > > Introduced RISC-V specific ELF definitions and hardware capability > detection. > Additionally, a function to retrieve hardware capabilities > ('get_elf_hwcap') is implemented, which returns the common bits set in > each CPU's ISA strings. > > Signed-off-by: Mark Corbin <mark.corbin@embecsom.com> > Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> > Co-authored-by: Kyle Evans <kevans@FreeBSD.org> > --- > bsd-user/riscv/target_arch_elf.h | 48 ++++++++++++++++++++++++++++++++ > 1 file changed, 48 insertions(+) > create mode 100644 bsd-user/riscv/target_arch_elf.h > > diff --git a/bsd-user/riscv/target_arch_elf.h b/bsd-user/riscv/target_arch_elf.h > new file mode 100644 > index 0000000000..dfb2a3e32e > --- /dev/null > +++ b/bsd-user/riscv/target_arch_elf.h > @@ -0,0 +1,48 @@ > +/* > + * RISC-V ELF definitions > + * > + * Copyright (c) 2019 Mark Corbin > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, see <http://www.gnu.org/licenses/>. > + */ > + > +#ifndef TARGET_ARCH_ELF_H > +#define TARGET_ARCH_ELF_H > + > +#define elf_check_arch(x) ((x) == EM_RISCV) > +#define ELF_START_MMAP 0x80000000 > +#define ELF_ET_DYN_LOAD_ADDR 0x100000 > +#define ELF_CLASS ELFCLASS64 > + > +#define ELF_DATA ELFDATA2LSB > +#define ELF_ARCH EM_RISCV > + > +/* > + * Note: FreeBSD returns things a litle differently than this, but this is as > + * close we have in the emulator. The FreeBSD/riscv64 kernel (in identcpu.c) > + * returns the common bits set in each of the CPUs' ISA strings. Also, unlike > + * linux, we don't mask out specific bits. Given that all user-only cpus are identical, all bits are common. So this really is identical to the freebsd kernel. I think that this comment is more confusing than illuminating. Otherwise, Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/bsd-user/riscv/target_arch_elf.h b/bsd-user/riscv/target_arch_elf.h new file mode 100644 index 0000000000..dfb2a3e32e --- /dev/null +++ b/bsd-user/riscv/target_arch_elf.h @@ -0,0 +1,48 @@ +/* + * RISC-V ELF definitions + * + * Copyright (c) 2019 Mark Corbin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef TARGET_ARCH_ELF_H +#define TARGET_ARCH_ELF_H + +#define elf_check_arch(x) ((x) == EM_RISCV) +#define ELF_START_MMAP 0x80000000 +#define ELF_ET_DYN_LOAD_ADDR 0x100000 +#define ELF_CLASS ELFCLASS64 + +#define ELF_DATA ELFDATA2LSB +#define ELF_ARCH EM_RISCV + +/* + * Note: FreeBSD returns things a litle differently than this, but this is as + * close we have in the emulator. The FreeBSD/riscv64 kernel (in identcpu.c) + * returns the common bits set in each of the CPUs' ISA strings. Also, unlike + * linux, we don't mask out specific bits. + */ +#define ELF_HWCAP get_elf_hwcap() +static uint32_t get_elf_hwcap(void) +{ + RISCVCPU *cpu = RISCV_CPU(thread_cpu); + + return cpu->env.misa_ext_mask; +} + +#define USE_ELF_CORE_DUMP +#define ELF_EXEC_PAGESIZE 4096 + +#endif /* TARGET_ARCH_ELF_H */