diff mbox series

[v2,06/13] target/riscv: Add select value range check for counter delegation

Message ID 20240723-counter_delegation-v2-6-c4170a5348ca@rivosinc.com (mailing list archive)
State New, archived
Headers show
Series Add RISC-V Counter delegation ISA extension support | expand

Commit Message

Atish Patra July 23, 2024, 11:30 p.m. UTC 
From: Kaiwen Xue <kaiwenx@rivosinc.com>

This adds checks in ops performed on xireg and xireg2-xireg6 so that the
counter delegation function will receive a valid xiselect value with the
proper extensions enabled.

Co-developed-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 target/riscv/csr.c | 36 +++++++++++++++++++++++++++++++++++-
 1 file changed, 35 insertions(+), 1 deletion(-)

Comments

Alistair Francis Aug. 6, 2024, 12:41 a.m. UTC | #1 
On Wed, Jul 24, 2024 at 9:31 AM Atish Patra <atishp@rivosinc.com> wrote:
>
> From: Kaiwen Xue <kaiwenx@rivosinc.com>
>
> This adds checks in ops performed on xireg and xireg2-xireg6 so that the
> counter delegation function will receive a valid xiselect value with the
> proper extensions enabled.
>
> Co-developed-by: Atish Patra <atishp@rivosinc.com>
> Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/csr.c | 36 +++++++++++++++++++++++++++++++++++-
>  1 file changed, 35 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 4ae3931f0ada..da27ba1b7580 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -2120,6 +2120,11 @@ static bool xiselect_aia_range(target_ulong isel)
>             (ISELECT_IMSIC_FIRST <= isel && isel <= ISELECT_IMSIC_LAST);
>  }
>
> +static bool xiselect_cd_range(target_ulong isel)
> +{
> +    return (ISELECT_CD_FIRST <= isel && isel <= ISELECT_CD_LAST);
> +}
> +
>  static int rmw_iprio(target_ulong xlen,
>                       target_ulong iselect, uint8_t *iprio,
>                       target_ulong *val, target_ulong new_val,
> @@ -2245,6 +2250,17 @@ done:
>      return RISCV_EXCP_NONE;
>  }
>
> +static int rmw_xireg_cd(CPURISCVState *env, int csrno,
> +                        target_ulong isel, target_ulong *val,
> +                        target_ulong new_val, target_ulong wr_mask)
> +{
> +    if (!riscv_cpu_cfg(env)->ext_smcdeleg) {
> +        return RISCV_EXCP_ILLEGAL_INST;
> +    }
> +    /* TODO: Implement the functionality later */
> +    return RISCV_EXCP_NONE;
> +}
> +
>  /*
>   * rmw_xireg_csrind: Perform indirect access to xireg and xireg2-xireg6
>   *
> @@ -2256,7 +2272,25 @@ static int rmw_xireg_csrind(CPURISCVState *env, int csrno,
>                                target_ulong isel, target_ulong *val,
>                                target_ulong new_val, target_ulong wr_mask)
>  {
> -    return -EINVAL;
> +    int ret = -EINVAL;
> +    bool virt = csrno == CSR_VSIREG ? true : false;
> +
> +    if (xiselect_cd_range(isel)) {
> +        ret = rmw_xireg_cd(env, csrno, isel, val, new_val, wr_mask);
> +    } else {
> +        /*
> +         * As per the specification, access to unimplented region is undefined
> +         * but recommendation is to raise illegal instruction exception.
> +         */
> +        return RISCV_EXCP_ILLEGAL_INST;
> +    }
> +
> +    if (ret) {
> +        return (env->virt_enabled && virt) ?
> +               RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
> +    }
> +
> +    return RISCV_EXCP_NONE;
>  }
>
>  static int rmw_xiregi(CPURISCVState *env, int csrno, target_ulong *val,
>
> --
> 2.34.1
>
>
diff mbox series

Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 4ae3931f0ada..da27ba1b7580 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -2120,6 +2120,11 @@  static bool xiselect_aia_range(target_ulong isel)
            (ISELECT_IMSIC_FIRST <= isel && isel <= ISELECT_IMSIC_LAST);
 }
 
+static bool xiselect_cd_range(target_ulong isel)
+{
+    return (ISELECT_CD_FIRST <= isel && isel <= ISELECT_CD_LAST);
+}
+
 static int rmw_iprio(target_ulong xlen,
                      target_ulong iselect, uint8_t *iprio,
                      target_ulong *val, target_ulong new_val,
@@ -2245,6 +2250,17 @@  done:
     return RISCV_EXCP_NONE;
 }
 
+static int rmw_xireg_cd(CPURISCVState *env, int csrno,
+                        target_ulong isel, target_ulong *val,
+                        target_ulong new_val, target_ulong wr_mask)
+{
+    if (!riscv_cpu_cfg(env)->ext_smcdeleg) {
+        return RISCV_EXCP_ILLEGAL_INST;
+    }
+    /* TODO: Implement the functionality later */
+    return RISCV_EXCP_NONE;
+}
+
 /*
  * rmw_xireg_csrind: Perform indirect access to xireg and xireg2-xireg6
  *
@@ -2256,7 +2272,25 @@  static int rmw_xireg_csrind(CPURISCVState *env, int csrno,
                               target_ulong isel, target_ulong *val,
                               target_ulong new_val, target_ulong wr_mask)
 {
-    return -EINVAL;
+    int ret = -EINVAL;
+    bool virt = csrno == CSR_VSIREG ? true : false;
+
+    if (xiselect_cd_range(isel)) {
+        ret = rmw_xireg_cd(env, csrno, isel, val, new_val, wr_mask);
+    } else {
+        /*
+         * As per the specification, access to unimplented region is undefined
+         * but recommendation is to raise illegal instruction exception.
+         */
+        return RISCV_EXCP_ILLEGAL_INST;
+    }
+
+    if (ret) {
+        return (env->virt_enabled && virt) ?
+               RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
+    }
+
+    return RISCV_EXCP_NONE;
 }
 
 static int rmw_xiregi(CPURISCVState *env, int csrno, target_ulong *val,