diff mbox series

[v2,10/13] target/riscv: Enable sscofpmf for bare cpu by default

Message ID 20240723-counter_delegation-v2-10-c4170a5348ca@rivosinc.com (mailing list archive)
State New, archived
Headers show
Series Add RISC-V Counter delegation ISA extension support | expand

Commit Message

Atish Kumar Patra July 23, 2024, 11:30 p.m. UTC
Sscofpmf has been supported on virt machine for a long time. It is
required to enable profiling on virt machines. Let's enable it
by default for ease of usage.

Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 target/riscv/cpu.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Alistair Francis Aug. 6, 2024, 1:51 a.m. UTC | #1
On Wed, Jul 24, 2024 at 9:33 AM Atish Patra <atishp@rivosinc.com> wrote:
>
> Sscofpmf has been supported on virt machine for a long time. It is
> required to enable profiling on virt machines. Let's enable it
> by default for ease of usage.
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
>  target/riscv/cpu.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1731dc461376..393d1d67120e 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -494,6 +494,7 @@ static void rv64_base_cpu_init(Object *obj)
>      env->priv_ver = PRIV_VERSION_LATEST;
>  #ifndef CONFIG_USER_ONLY
>      set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
> +    cpu->cfg.ext_sscofpmf = true;

Unfortunately we don't want to do this, the base CPU should be bare
bones and then users can enable extensions.

Alistair

>  #endif
>  }
>
>
> --
> 2.34.1
>
>
Andrew Jones Aug. 6, 2024, 8:27 a.m. UTC | #2
On Tue, Aug 06, 2024 at 11:51:20AM GMT, Alistair Francis wrote:
> On Wed, Jul 24, 2024 at 9:33 AM Atish Patra <atishp@rivosinc.com> wrote:
> >
> > Sscofpmf has been supported on virt machine for a long time. It is
> > required to enable profiling on virt machines. Let's enable it
> > by default for ease of usage.
> >
> > Signed-off-by: Atish Patra <atishp@rivosinc.com>
> > ---
> >  target/riscv/cpu.c | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 1731dc461376..393d1d67120e 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -494,6 +494,7 @@ static void rv64_base_cpu_init(Object *obj)
> >      env->priv_ver = PRIV_VERSION_LATEST;
> >  #ifndef CONFIG_USER_ONLY
> >      set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
> > +    cpu->cfg.ext_sscofpmf = true;
> 
> Unfortunately we don't want to do this, the base CPU should be bare
> bones and then users can enable extensions.

But we do want to enable stuff by default in the 'max' cpu type.

Thanks,
drew
diff mbox series

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1731dc461376..393d1d67120e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -494,6 +494,7 @@  static void rv64_base_cpu_init(Object *obj)
     env->priv_ver = PRIV_VERSION_LATEST;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
+    cpu->cfg.ext_sscofpmf = true;
 #endif
 }