| Message ID | 20240730125023.710237-3-jbrunet@baylibre.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/meson: dw-hdmi: clean-up | expand |
On Tue, Jul 30, 2024 at 2:50 PM Jerome Brunet <jbrunet@baylibre.com> wrote: > > Poking the HHI syscon is a way to setup clocks behind CCF's back. > Also, 2 drm code paths, the encoder and the hdmi-phy, are racing to do the > same setup of the HDMI system clock. > > This clock is used is used by the HDMI phy and should not be set by the > encoder, so drop those HHI pokes from vclk. > > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
On 30/07/2024 14:50, Jerome Brunet wrote: > Poking the HHI syscon is a way to setup clocks behind CCF's back. > Also, 2 drm code paths, the encoder and the hdmi-phy, are racing to do the > same setup of the HDMI system clock. > > This clock is used is used by the HDMI phy and should not be set by the > encoder, so drop those HHI pokes from vclk. > > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> > --- > drivers/gpu/drm/meson/meson_vclk.c | 8 -------- > 1 file changed, 8 deletions(-) > > diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c > index 2a942dc6a6dc..bf5cc5d92346 100644 > --- a/drivers/gpu/drm/meson/meson_vclk.c > +++ b/drivers/gpu/drm/meson/meson_vclk.c > @@ -813,14 +813,6 @@ static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq, > { > unsigned int m = 0, frac = 0; > > - /* Set HDMI-TX sys clock */ > - regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, > - CTS_HDMI_SYS_SEL_MASK, 0); > - regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, > - CTS_HDMI_SYS_DIV_MASK, 0); > - regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, > - CTS_HDMI_SYS_EN, CTS_HDMI_SYS_EN); > - > /* Set HDMI PLL rate */ > if (!od1 && !od2 && !od3) { > meson_hdmi_pll_generic_set(priv, pll_base_freq); Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c index 2a942dc6a6dc..bf5cc5d92346 100644 --- a/drivers/gpu/drm/meson/meson_vclk.c +++ b/drivers/gpu/drm/meson/meson_vclk.c @@ -813,14 +813,6 @@ static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq, { unsigned int m = 0, frac = 0; - /* Set HDMI-TX sys clock */ - regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, - CTS_HDMI_SYS_SEL_MASK, 0); - regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, - CTS_HDMI_SYS_DIV_MASK, 0); - regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, - CTS_HDMI_SYS_EN, CTS_HDMI_SYS_EN); - /* Set HDMI PLL rate */ if (!od1 && !od2 && !od3) { meson_hdmi_pll_generic_set(priv, pll_base_freq);
Poking the HHI syscon is a way to setup clocks behind CCF's back. Also, 2 drm code paths, the encoder and the hdmi-phy, are racing to do the same setup of the HDMI system clock. This clock is used is used by the HDMI phy and should not be set by the encoder, so drop those HHI pokes from vclk. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> --- drivers/gpu/drm/meson/meson_vclk.c | 8 -------- 1 file changed, 8 deletions(-)