diff mbox series

[RFC,04/23] hw/arm: add SVD file for NXP i.MX RT595

Message ID 20240805201719.2345596-5-tavip@google.com (mailing list archive)
State New, archived
Headers show
Series NXP i.MX RT595, ARM SVD and device model unit tests | expand

Commit Message

Octavian Purdila Aug. 5, 2024, 8:16 p.m. UTC 
Picked from:

https://github.com/nxp-mcuxpresso/mcux-soc-svd/blob/main/MIMXRT595S/MIMXRT595S_cm33.xml

NOTE: the file is truncated to keep the email size reasonable. Please
use the link above and download the full file if you want to try out
the patch.

Signed-off-by: Octavian Purdila <tavip@google.com>
---
 hw/arm/svd/MIMXRT595S_cm33.xml | 224052 ++++++++++++++++++++++++++++++
 1 file changed, 224052 insertions(+)
 create mode 100644 hw/arm/svd/MIMXRT595S_cm33.xml

Comments

Alex Bennée Aug. 6, 2024, 2:06 p.m. UTC | #1 
Octavian Purdila <tavip@google.com> writes:

> Picked from:
>
> https://github.com/nxp-mcuxpresso/mcux-soc-svd/blob/main/MIMXRT595S/MIMXRT595S_cm33.xml
>
> NOTE: the file is truncated to keep the email size reasonable. Please
> use the link above and download the full file if you want to try out
> the patch.
>
> Signed-off-by: Octavian Purdila <tavip@google.com>
> ---
>  hw/arm/svd/MIMXRT595S_cm33.xml | 224052
> ++++++++++++++++++++++++++++++

I guess one thing we need to decide is if the source XML should live in
the repository as the preferred method of making changes or just the
translations generated by the tool.

>  1 file changed, 224052 insertions(+)
>  create mode 100644 hw/arm/svd/MIMXRT595S_cm33.xml
>
> diff --git a/hw/arm/svd/MIMXRT595S_cm33.xml b/hw/arm/svd/MIMXRT595S_cm33.xml
> new file mode 100644
> index 0000000000..8943aa3555
> --- /dev/null
> +++ b/hw/arm/svd/MIMXRT595S_cm33.xml
> @@ -0,0 +1,1725 @@
> +<?xml version="1.0" encoding="UTF-8"?>
> +<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
> +  <vendor>nxp.com</vendor>
> +  <name>MIMXRT595S_cm33</name>
> +  <version>1.0</version>
> +  <description>MIMXRT595SFAWC,MIMXRT595SFFOC</description>
> +  <licenseText>
> +Copyright 2016-2023 NXP
> +SPDX-License-Identifier: BSD-3-Clause
> +  </licenseText>

This certainly seems compatible. XML is not the medium I personally
would have chosen as a register specification language but I guess there
are no other alternatives?
Octavian Purdila Aug. 6, 2024, 8:31 p.m. UTC | #2 
On Tue, Aug 6, 2024 at 7:06 AM Alex Bennée <alex.bennee@linaro.org> wrote:
>
> Octavian Purdila <tavip@google.com> writes:
>
> > Picked from:
> >
> > https://github.com/nxp-mcuxpresso/mcux-soc-svd/blob/main/MIMXRT595S/MIMXRT595S_cm33.xml
> >
> > NOTE: the file is truncated to keep the email size reasonable. Please
> > use the link above and download the full file if you want to try out
> > the patch.
> >
> > Signed-off-by: Octavian Purdila <tavip@google.com>
> > ---
> >  hw/arm/svd/MIMXRT595S_cm33.xml | 224052
> > ++++++++++++++++++++++++++++++
>
> I guess one thing we need to decide is if the source XML should live in
> the repository as the preferred method of making changes or just the
> translations generated by the tool.
>

I think we might want to store the XML in the qemu repo, even if we
don't use it to generate the header files at compile time. This avoids
issues with the original XML moving, going away, changed in
incompatible ways, etc.

As for generating the headers at compile time, I don't have a strong
preference. I like it because there is slightly less work to do and it
avoids dealing with resolving changes on both the SVD and the
generated headers. For example, the initial headers are committed,
then some changes are done directly to the headers and then we want to
pick up a new SVD from the vendor to support a new hardware revision.

There are disadvantages as well: pysvd dependency for building qemu,
hard to review if the vendor dumps a new version with lots of changes
and we want to update to it for a new hardware revision, slight
increase in build time.

> >  1 file changed, 224052 insertions(+)
> >  create mode 100644 hw/arm/svd/MIMXRT595S_cm33.xml
> >
> > diff --git a/hw/arm/svd/MIMXRT595S_cm33.xml b/hw/arm/svd/MIMXRT595S_cm33.xml
> > new file mode 100644
> > index 0000000000..8943aa3555
> > --- /dev/null
> > +++ b/hw/arm/svd/MIMXRT595S_cm33.xml
> > @@ -0,0 +1,1725 @@
> > +<?xml version="1.0" encoding="UTF-8"?>
> > +<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
> > +  <vendor>nxp.com</vendor>
> > +  <name>MIMXRT595S_cm33</name>
> > +  <version>1.0</version>
> > +  <description>MIMXRT595SFAWC,MIMXRT595SFFOC</description>
> > +  <licenseText>
> > +Copyright 2016-2023 NXP
> > +SPDX-License-Identifier: BSD-3-Clause
> > +  </licenseText>
>
> This certainly seems compatible. XML is not the medium I personally
> would have chosen as a register specification language but I guess there
> are no other alternatives?
>

I agree that the choice of XML is unfortunate but I am not aware of
alternatives, this is what vendors will provide.
Philippe Mathieu-Daudé Aug. 7, 2024, 11:24 a.m. UTC | #3 
On 6/8/24 22:31, Octavian Purdila wrote:
> On Tue, Aug 6, 2024 at 7:06 AM Alex Bennée <alex.bennee@linaro.org> wrote:
>>
>> Octavian Purdila <tavip@google.com> writes:
>>
>>> Picked from:
>>>
>>> https://github.com/nxp-mcuxpresso/mcux-soc-svd/blob/main/MIMXRT595S/MIMXRT595S_cm33.xml
>>>
>>> NOTE: the file is truncated to keep the email size reasonable. Please
>>> use the link above and download the full file if you want to try out
>>> the patch.
>>>
>>> Signed-off-by: Octavian Purdila <tavip@google.com>
>>> ---
>>>   hw/arm/svd/MIMXRT595S_cm33.xml | 224052
>>> ++++++++++++++++++++++++++++++
>>
>> I guess one thing we need to decide is if the source XML should live in
>> the repository as the preferred method of making changes or just the
>> translations generated by the tool.
>>
> 
> I think we might want to store the XML in the qemu repo, even if we
> don't use it to generate the header files at compile time. This avoids
> issues with the original XML moving, going away, changed in
> incompatible ways, etc.

Until now we tracked external sources with git submodules or meson
wrap files (see commit 2019cabfee) forked into our GitLab namespace
(https://gitlab.com/qemu-project/) at a particular commit, so if
the external project is modified, we aren't disturbed, or have to
adapt our source to update the submodule. Isn't it good enough?

> 
> As for generating the headers at compile time, I don't have a strong
> preference. I like it because there is slightly less work to do and it
> avoids dealing with resolving changes on both the SVD and the
> generated headers. For example, the initial headers are committed,
> then some changes are done directly to the headers and then we want to
> pick up a new SVD from the vendor to support a new hardware revision.
> 
> There are disadvantages as well: pysvd dependency for building qemu,
> hard to review if the vendor dumps a new version with lots of changes
> and we want to update to it for a new hardware revision, slight
> increase in build time.
> 
>>>   1 file changed, 224052 insertions(+)
>>>   create mode 100644 hw/arm/svd/MIMXRT595S_cm33.xml
>>>
>>> diff --git a/hw/arm/svd/MIMXRT595S_cm33.xml b/hw/arm/svd/MIMXRT595S_cm33.xml
>>> new file mode 100644
>>> index 0000000000..8943aa3555
>>> --- /dev/null
>>> +++ b/hw/arm/svd/MIMXRT595S_cm33.xml
>>> @@ -0,0 +1,1725 @@
>>> +<?xml version="1.0" encoding="UTF-8"?>
>>> +<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
>>> +  <vendor>nxp.com</vendor>
>>> +  <name>MIMXRT595S_cm33</name>
>>> +  <version>1.0</version>
>>> +  <description>MIMXRT595SFAWC,MIMXRT595SFFOC</description>
>>> +  <licenseText>
>>> +Copyright 2016-2023 NXP
>>> +SPDX-License-Identifier: BSD-3-Clause
>>> +  </licenseText>
>>
>> This certainly seems compatible. XML is not the medium I personally
>> would have chosen as a register specification language but I guess there
>> are no other alternatives?
>>
> 
> I agree that the choice of XML is unfortunate but I am not aware of
> alternatives, this is what vendors will provide.
Octavian Purdila Aug. 7, 2024, 4:36 p.m. UTC | #4 
On Wed, Aug 7, 2024 at 4:24 AM Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
>
> On 6/8/24 22:31, Octavian Purdila wrote:
> > On Tue, Aug 6, 2024 at 7:06 AM Alex Bennée <alex.bennee@linaro.org> wrote:
> >>
> >> Octavian Purdila <tavip@google.com> writes:
> >>
> >>> Picked from:
> >>>
> >>> https://github.com/nxp-mcuxpresso/mcux-soc-svd/blob/main/MIMXRT595S/MIMXRT595S_cm33.xml
> >>>
> >>> NOTE: the file is truncated to keep the email size reasonable. Please
> >>> use the link above and download the full file if you want to try out
> >>> the patch.
> >>>
> >>> Signed-off-by: Octavian Purdila <tavip@google.com>
> >>> ---
> >>>   hw/arm/svd/MIMXRT595S_cm33.xml | 224052
> >>> ++++++++++++++++++++++++++++++
> >>
> >> I guess one thing we need to decide is if the source XML should live in
> >> the repository as the preferred method of making changes or just the
> >> translations generated by the tool.
> >>
> >
> > I think we might want to store the XML in the qemu repo, even if we
> > don't use it to generate the header files at compile time. This avoids
> > issues with the original XML moving, going away, changed in
> > incompatible ways, etc.
>
> Until now we tracked external sources with git submodules or meson
> wrap files (see commit 2019cabfee) forked into our GitLab namespace
> (https://gitlab.com/qemu-project/) at a particular commit, so if
> the external project is modified, we aren't disturbed, or have to
> adapt our source to update the submodule. Isn't it good enough?
>

Yes, this should definitely work. Thanks for pointing out the wrap
files, I'll give it a try.

> >
> > As for generating the headers at compile time, I don't have a strong
> > preference. I like it because there is slightly less work to do and it
> > avoids dealing with resolving changes on both the SVD and the
> > generated headers. For example, the initial headers are committed,
> > then some changes are done directly to the headers and then we want to
> > pick up a new SVD from the vendor to support a new hardware revision.
> >
> > There are disadvantages as well: pysvd dependency for building qemu,
> > hard to review if the vendor dumps a new version with lots of changes
> > and we want to update to it for a new hardware revision, slight
> > increase in build time.
> >
> >>>   1 file changed, 224052 insertions(+)
> >>>   create mode 100644 hw/arm/svd/MIMXRT595S_cm33.xml
> >>>
> >>> diff --git a/hw/arm/svd/MIMXRT595S_cm33.xml b/hw/arm/svd/MIMXRT595S_cm33.xml
> >>> new file mode 100644
> >>> index 0000000000..8943aa3555
> >>> --- /dev/null
> >>> +++ b/hw/arm/svd/MIMXRT595S_cm33.xml
> >>> @@ -0,0 +1,1725 @@
> >>> +<?xml version="1.0" encoding="UTF-8"?>
> >>> +<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
> >>> +  <vendor>nxp.com</vendor>
> >>> +  <name>MIMXRT595S_cm33</name>
> >>> +  <version>1.0</version>
> >>> +  <description>MIMXRT595SFAWC,MIMXRT595SFFOC</description>
> >>> +  <licenseText>
> >>> +Copyright 2016-2023 NXP
> >>> +SPDX-License-Identifier: BSD-3-Clause
> >>> +  </licenseText>
> >>
> >> This certainly seems compatible. XML is not the medium I personally
> >> would have chosen as a register specification language but I guess there
> >> are no other alternatives?
> >>
> >
> > I agree that the choice of XML is unfortunate but I am not aware of
> > alternatives, this is what vendors will provide.
>
Daniel P. Berrangé Aug. 9, 2024, 9:13 a.m. UTC | #5 
On Tue, Aug 06, 2024 at 01:31:51PM -0700, Octavian Purdila wrote:
> On Tue, Aug 6, 2024 at 7:06 AM Alex Bennée <alex.bennee@linaro.org> wrote:
> >
> > Octavian Purdila <tavip@google.com> writes:
> >
> > > Picked from:
> > >
> > > https://github.com/nxp-mcuxpresso/mcux-soc-svd/blob/main/MIMXRT595S/MIMXRT595S_cm33.xml
> > >
> > > NOTE: the file is truncated to keep the email size reasonable. Please
> > > use the link above and download the full file if you want to try out
> > > the patch.

"the file is truncated" wins understatement of the week.

The full XML file that would need to be in QEMU git for this is 8.6 MB in
size.

The overall generated headers that we get from it are ~16k lines,
or ~0.5 MB

$ wc -l build/hw/arm/svd/*.h
   135 build/hw/arm/svd/flexcomm.h
  1227 build/hw/arm/svd/flexcomm_i2c.h
  1161 build/hw/arm/svd/flexcomm_spi.h
  1231 build/hw/arm/svd/flexcomm_usart.h
  2243 build/hw/arm/svd/flexspi.h
  3100 build/hw/arm/svd/rt500_clkctl0.h
  4022 build/hw/arm/svd/rt500_clkctl1.h
    64 build/hw/arm/svd/rt500.h
  1073 build/hw/arm/svd/rt500_rstctl0.h
  1697 build/hw/arm/svd/rt500_rstctl1.h
 15953 total

$ wc -c build/hw/arm/svd/*.h
  4349 build/hw/arm/svd/flexcomm.h
 51135 build/hw/arm/svd/flexcomm_i2c.h
 43822 build/hw/arm/svd/flexcomm_spi.h
 46331 build/hw/arm/svd/flexcomm_usart.h
 89224 build/hw/arm/svd/flexspi.h
113952 build/hw/arm/svd/rt500_clkctl0.h
141885 build/hw/arm/svd/rt500_clkctl1.h
  1881 build/hw/arm/svd/rt500.h
 38881 build/hw/arm/svd/rt500_rstctl0.h
 61449 build/hw/arm/svd/rt500_rstctl1.h
592909 total



> > >
> > > Signed-off-by: Octavian Purdila <tavip@google.com>
> > > ---
> > >  hw/arm/svd/MIMXRT595S_cm33.xml | 224052
> > > ++++++++++++++++++++++++++++++
> >
> > I guess one thing we need to decide is if the source XML should live in
> > the repository as the preferred method of making changes or just the
> > translations generated by the tool.
> >
> 
> I think we might want to store the XML in the qemu repo, even if we
> don't use it to generate the header files at compile time. This avoids
> issues with the original XML moving, going away, changed in
> incompatible ways, etc.
>
> As for generating the headers at compile time, I don't have a strong
> preference. I like it because there is slightly less work to do and it
> avoids dealing with resolving changes on both the SVD and the
> generated headers. For example, the initial headers are committed,
> then some changes are done directly to the headers and then we want to
> pick up a new SVD from the vendor to support a new hardware revision.

IIUC the structs/enums/etc are defining guest ABI. So if we want to
preserve guest ABI for these devices across QEMU releases, we don't
want the generated output to be arbitrarily changing. If there are
different revisions of a device, we might need separate structs for
each maintained in parallel.



> 
> There are disadvantages as well: pysvd dependency for building qemu,
> hard to review if the vendor dumps a new version with lots of changes
> and we want to update to it for a new hardware revision, slight
> increase in build time.
> 
> > >  1 file changed, 224052 insertions(+)
> > >  create mode 100644 hw/arm/svd/MIMXRT595S_cm33.xml
> > >
> > > diff --git a/hw/arm/svd/MIMXRT595S_cm33.xml b/hw/arm/svd/MIMXRT595S_cm33.xml
> > > new file mode 100644
> > > index 0000000000..8943aa3555
> > > --- /dev/null
> > > +++ b/hw/arm/svd/MIMXRT595S_cm33.xml
> > > @@ -0,0 +1,1725 @@
> > > +<?xml version="1.0" encoding="UTF-8"?>
> > > +<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
> > > +  <vendor>nxp.com</vendor>
> > > +  <name>MIMXRT595S_cm33</name>
> > > +  <version>1.0</version>
> > > +  <description>MIMXRT595SFAWC,MIMXRT595SFFOC</description>
> > > +  <licenseText>
> > > +Copyright 2016-2023 NXP
> > > +SPDX-License-Identifier: BSD-3-Clause
> > > +  </licenseText>
> >
> > This certainly seems compatible. XML is not the medium I personally
> > would have chosen as a register specification language but I guess there
> > are no other alternatives?
> >
> 
> I agree that the choice of XML is unfortunate but I am not aware of
> alternatives, this is what vendors will provide.

Given the size of the XML I'm inclined to say that we should just be
committing the generated header files to qemu.git

Then add https://github.com/nxp-mcuxpresso/mcux-soc-svd as a git
submodule, and provide some meson rules for triggering re-generation
that are off-by-default.

With regards,
Daniel
Octavian Purdila Aug. 9, 2024, 10:40 p.m. UTC | #6 
On Fri, Aug 9, 2024 at 2:13 AM Daniel P. Berrangé <berrange@redhat.com> wrote:
>
> On Tue, Aug 06, 2024 at 01:31:51PM -0700, Octavian Purdila wrote:
> > On Tue, Aug 6, 2024 at 7:06 AM Alex Bennée <alex.bennee@linaro.org> wrote:
> > >
> > > Octavian Purdila <tavip@google.com> writes:
> > >
> > > > Picked from:
> > > >
> > > > https://github.com/nxp-mcuxpresso/mcux-soc-svd/blob/main/MIMXRT595S/MIMXRT595S_cm33.xml
> > > >
> > > > NOTE: the file is truncated to keep the email size reasonable. Please
> > > > use the link above and download the full file if you want to try out
> > > > the patch.
>
> "the file is truncated" wins understatement of the week.
>
> The full XML file that would need to be in QEMU git for this is 8.6 MB in
> size.
>
> The overall generated headers that we get from it are ~16k lines,
> or ~0.5 MB
>
> $ wc -l build/hw/arm/svd/*.h
>    135 build/hw/arm/svd/flexcomm.h
>   1227 build/hw/arm/svd/flexcomm_i2c.h
>   1161 build/hw/arm/svd/flexcomm_spi.h
>   1231 build/hw/arm/svd/flexcomm_usart.h
>   2243 build/hw/arm/svd/flexspi.h
>   3100 build/hw/arm/svd/rt500_clkctl0.h
>   4022 build/hw/arm/svd/rt500_clkctl1.h
>     64 build/hw/arm/svd/rt500.h
>   1073 build/hw/arm/svd/rt500_rstctl0.h
>   1697 build/hw/arm/svd/rt500_rstctl1.h
>  15953 total
>
> $ wc -c build/hw/arm/svd/*.h
>   4349 build/hw/arm/svd/flexcomm.h
>  51135 build/hw/arm/svd/flexcomm_i2c.h
>  43822 build/hw/arm/svd/flexcomm_spi.h
>  46331 build/hw/arm/svd/flexcomm_usart.h
>  89224 build/hw/arm/svd/flexspi.h
> 113952 build/hw/arm/svd/rt500_clkctl0.h
> 141885 build/hw/arm/svd/rt500_clkctl1.h
>   1881 build/hw/arm/svd/rt500.h
>  38881 build/hw/arm/svd/rt500_rstctl0.h
>  61449 build/hw/arm/svd/rt500_rstctl1.h
> 592909 total
>
>
>
> > > >
> > > > Signed-off-by: Octavian Purdila <tavip@google.com>
> > > > ---
> > > >  hw/arm/svd/MIMXRT595S_cm33.xml | 224052
> > > > ++++++++++++++++++++++++++++++
> > >
> > > I guess one thing we need to decide is if the source XML should live in
> > > the repository as the preferred method of making changes or just the
> > > translations generated by the tool.
> > >
> >
> > I think we might want to store the XML in the qemu repo, even if we
> > don't use it to generate the header files at compile time. This avoids
> > issues with the original XML moving, going away, changed in
> > incompatible ways, etc.
> >
> > As for generating the headers at compile time, I don't have a strong
> > preference. I like it because there is slightly less work to do and it
> > avoids dealing with resolving changes on both the SVD and the
> > generated headers. For example, the initial headers are committed,
> > then some changes are done directly to the headers and then we want to
> > pick up a new SVD from the vendor to support a new hardware revision.
>
> IIUC the structs/enums/etc are defining guest ABI. So if we want to
> preserve guest ABI for these devices across QEMU releases, we don't
> want the generated output to be arbitrarily changing. If there are
> different revisions of a device, we might need separate structs for
> each maintained in parallel.
>

I think we can review changes to prevent ABI breakages both for XML
and generated headers - unless we use meson git-wrap submodules.

>
>
> >
> > There are disadvantages as well: pysvd dependency for building qemu,
> > hard to review if the vendor dumps a new version with lots of changes
> > and we want to update to it for a new hardware revision, slight
> > increase in build time.
> >
> > > >  1 file changed, 224052 insertions(+)
> > > >  create mode 100644 hw/arm/svd/MIMXRT595S_cm33.xml
> > > >
> > > > diff --git a/hw/arm/svd/MIMXRT595S_cm33.xml b/hw/arm/svd/MIMXRT595S_cm33.xml
> > > > new file mode 100644
> > > > index 0000000000..8943aa3555
> > > > --- /dev/null
> > > > +++ b/hw/arm/svd/MIMXRT595S_cm33.xml
> > > > @@ -0,0 +1,1725 @@
> > > > +<?xml version="1.0" encoding="UTF-8"?>
> > > > +<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
> > > > +  <vendor>nxp.com</vendor>
> > > > +  <name>MIMXRT595S_cm33</name>
> > > > +  <version>1.0</version>
> > > > +  <description>MIMXRT595SFAWC,MIMXRT595SFFOC</description>
> > > > +  <licenseText>
> > > > +Copyright 2016-2023 NXP
> > > > +SPDX-License-Identifier: BSD-3-Clause
> > > > +  </licenseText>
> > >
> > > This certainly seems compatible. XML is not the medium I personally
> > > would have chosen as a register specification language but I guess there
> > > are no other alternatives?
> > >
> >
> > I agree that the choice of XML is unfortunate but I am not aware of
> > alternatives, this is what vendors will provide.
>
> Given the size of the XML I'm inclined to say that we should just be
> committing the generated header files to qemu.git
>

Fine with me. I think we can also reconsider later with minimal effort
if this gets widely used and there is lots of churn.

Peter, what do you think?

> Then add https://github.com/nxp-mcuxpresso/mcux-soc-svd as a git
> submodule, and provide some meson rules for triggering re-generation
> that are off-by-default.
>

Sounds good. I was thinking of adding mcux-soc-svd as a meson
subproject via git-wrap as suggested by Philippe.



> With regards,
> Daniel
> --
> |: https://berrange.com      -o-    https://www.flickr.com/photos/dberrange :|
> |: https://libvirt.org         -o-            https://fstop138.berrange.com :|
> |: https://entangle-photo.org    -o-    https://www.instagram.com/dberrange :|
>
diff mbox series

Patch

diff --git a/hw/arm/svd/MIMXRT595S_cm33.xml b/hw/arm/svd/MIMXRT595S_cm33.xml
new file mode 100644
index 0000000000..8943aa3555
--- /dev/null
+++ b/hw/arm/svd/MIMXRT595S_cm33.xml
@@ -0,0 +1,1725 @@ 
+<?xml version="1.0" encoding="UTF-8"?>
+<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
+  <vendor>nxp.com</vendor>
+  <name>MIMXRT595S_cm33</name>
+  <version>1.0</version>
+  <description>MIMXRT595SFAWC,MIMXRT595SFFOC</description>
+  <licenseText>
+Copyright 2016-2023 NXP
+SPDX-License-Identifier: BSD-3-Clause
+  </licenseText>
+  <cpu>
+    <name>CM33</name>
+    <revision>r2p0</revision>
+    <endian>little</endian>
+    <mpuPresent>true</mpuPresent>
+    <fpuPresent>true</fpuPresent>
+    <vtorPresent>true</vtorPresent>
+    <nvicPrioBits>3</nvicPrioBits>
+    <vendorSystickConfig>false</vendorSystickConfig>
+  </cpu>
+  <addressUnitBits>8</addressUnitBits>
+  <width>32</width>
+  <peripherals>
+    <peripheral>
+      <name>RSTCTL0</name>
+      <description>Reset Controller 0</description>
+      <groupName>RSTCTL0</groupName>
+      <baseAddress>0x40000000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x7C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SYSRSTSTAT</name>
+          <description>System Reset Status Register</description>
+          <addressOffset>0</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x1</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>VDD_POR</name>
+              <description>VDD CORE Power-On Reset (POR) was detected</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>VDD_POR_EVENT_IS_NOT_DETECTED</name>
+                  <description>No VDD CORE POR event is detected</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>VDD_POR_EVENT_WAS_DETECTED</name>
+                  <description>VDD CORE POR event was detected</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PAD_RESET</name>
+              <description>RESETN pin reset was detected</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PAD_RESET_IS_NOT_DETECTED</name>
+                  <description>No RESETN pin event is detected</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PAD_RESET_WAS_DETECTED</name>
+                  <description>RESETN pin event was detected. Write '1' to clear this bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ARM_RESET</name>
+              <description>ARM reset was detected</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>ARM_RESET_IS_NOT_DETECTED</name>
+                  <description>No ARM reset event is detected</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ARM_RESET_WAS_DETECTED</name>
+                  <description>ARM reset was detected. Write '1' to clear this bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WDT0_RESET</name>
+              <description>WatchDog Timer 0 reset was detected</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>WDT0_RESET_IS_NOT_DETECTED</name>
+                  <description>No WDT0 reset event detected</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WDT0_RESET_WAS_DETECTED</name>
+                  <description>WDT0 reset event detected. Write '1' to clear this bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WDT1_RESET</name>
+              <description>WatchDog Timer 1 reset was detected</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>WDT1_RESET_IS_NOT_DETECTED</name>
+                  <description>No WDT1 reset event detected</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WDT1_RESET_WAS_DETECTED</name>
+                  <description>WDT1 reset event detected. Write '1' to clear this bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRSTCTL0</name>
+          <description>Peripheral Reset Control Register 0</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x7DF51F0A</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>DSP</name>
+              <description>Fusion F1 DSP reset control</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>DSP_CLR</name>
+                  <description>Clear Reset</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSP_SET</name>
+                  <description>Set Reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AXI_SWITCH</name>
+              <description>AXI Switch reset control</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>AXI_SWITCH_CLR</name>
+                  <description>Clear Reset</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AXI_SWITCH_SET</name>
+                  <description>Set Reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>POWERQUAD</name>
+              <description>POWERQUAD reset control</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>POWERQUAD_CLR</name>
+                  <description>Clear Reset</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>POWERQUAD_SET</name>
+                  <description>Set Reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CASPER</name>
+              <description>CASPER reset control</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>CASPER_CLR</name>
+                  <description>Clear Reset</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CASPER_SET</name>
+                  <description>Set Reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>HASHCRYPT</name>
+              <description>Hash-Crypt reset control</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>HASHCRYPT_CLR</name>
+                  <description>Clear Reset</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HASHCRYPT_SET</name>
+                  <description>Set Reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PUF</name>
+              <description>PUF reset control</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PUF_CLR</name>
+                  <description>Clear Reset</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PUF_SET</name>
+                  <description>Set Reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RNG</name>
+              <description>RNG reset control</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>RNG_CLR</name>
+                  <description>Clear Reset</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RNG_SET</name>
+                  <description>Set Reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FLEXSPI0_OTFAD</name>
+              <description>FLEXSPI0 and OTFAD reset control</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>FLEXSPI0_OTFAD_CLR</name>
+                  <description>Clear Reset</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FLEXSPI0_OTFAD_SET</name>
+                  <description>Set Reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FLEXSPI1</name>
+              <description>FLEXSPI1 reset control</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>FLEXSPI1_CLR</name>
+                  <description>Clear Reset</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FLEXSPI1_SET</name>
+                  <description>Set Reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>USBHS_PHY</name>
+              <description>USB PHY reset control</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>USBHS_PHY_CLR</name>
+                  <description>Clear Reset</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USBHS_PHY_SET</name>
+                  <description>Set Reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>USBHS_DEVICE</name>
+              <description>USB HS Device reset control</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>USBHS_DEVICE_CLR</name>
+                  <description>Clear Reset</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USBHS_DEVICE_SET</name>
+                  <description>Set Reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>USBHS_HOST</name>
+              <description>USB HOST reset control</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>USBHS_HOST_CLR</name>
+                  <description>Clear Reset</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USBHS_HOST_SET</name>
+                  <description>Set Reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>USBHS_SRAM</name>
+              <description>USB RAM reset control</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>USBHS_SRAM_CLR</name>
+                  <description>Clear Reset</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USBHS_SRAM_SET</name>
+                  <description>Set Reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SCT</name>
+              <description>SCTimer reset control</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>SCT_CLR</name>
+                  <description>Clear Reset</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCT_SET</name>
+                  <description>Set Reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GPU</name>
+              <description>GPU reset control</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>GPU_CLR</name>
+                  <description>Clear Reset</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPU_SET</name>
+                  <description>Set Reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DISPLAY_CONTROLLER</name>
+              <description>LCDIF Display Controller reset control</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>DISPLAY_CONTROLLER_CLR</name>
+                  <description>Clear Reset</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DISPLAY_CONTROLLER_SET</name>
+                  <description>Set Reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MIPI_DSI_CONTROLLER</name>
+              <description>MIPI Digital serial Interface controller reset control</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>MIPI_DSI_CONTROLLER_CLR</name>
+                  <description>Clear Reset</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MIPI_DSI_CONTROLLER_SET</name>
+                  <description>Set Reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MIPI_DSI_PHY</name>
+              <description>MIPI DSI PHY reset control</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>MIPI_DSI_PHY_CLR</name>
+                  <description>Clear Reset</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MIPI_DSI_PHY_SET</name>
+                  <description>Set Reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SMARTDMA</name>
+              <description>SMARTDMA Event/Algorithm handler reset control</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>SMARTDMA_CLR</name>
+                  <description>Clear Reset</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SMARTDMA_SET</name>
+                  <description>Set Reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRSTCTL1</name>
+          <description>Peripheral Reset Control Register 1</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x101800C</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>SDIO0</name>
+              <description>SDIO0 reset control</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>SDIO0_CLR</name>
+                  <description>Clear Reset</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SDIO0_SET</name>
+                  <description>Set Reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SDIO1</name>
+              <description>SDIO1 reset control</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>SDIO1_CLR</name>
+                  <description>Clear Reset</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SDIO1_SET</name>
+                  <description>Set Reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ACMP0</name>
+              <description>Analog comparator reset control</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>ACMP0_CLR</name>
+                  <description>Clear Reset</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ACMP0_SET</name>
+                  <description>Set Reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADC0</name>
+              <description>Analog-to-Digital converter reset control</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>ADC0_CLR</name>
+                  <description>Clear Reset</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ADC0_SET</name>
+                  <description>Set Reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SHSGPIO0</name>
+              <description>Secure GPIO 0 reset control</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>SHSGPIO0_CLR</name>
+                  <description>Clear Reset</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SHSGPIO0_SET</name>
+                  <description>Set Reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRSTCTL2</name>
+          <description>Peripheral Reset Control Register 2</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x1C000001</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>UTICK0</name>
+              <description>Micro-tick timer reset control</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>UTICK0_CLR</name>
+                  <description>Clear Reset</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UTICK0_SET</name>
+                  <description>Set Reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WWDT0</name>
+              <description>Watchdog timer reset control</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>WWDT0_CLR</name>
+                  <description>Clear Reset</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WWDT0_SET</name>
+                  <description>Set Reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRSTCTL0_SET</name>
+          <description>Peripheral Reset Control Register 0 SET</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>DSP</name>
+              <description>Fusion_ DSP reset set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>DSP_CLR</name>
+                  <description>No Effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSP_SET</name>
+                  <description>Sets the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AXI_SWITCH</name>
+              <description>AXI SWITCH reset set</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>AXI_SWITCH_CLR</name>
+                  <description>No Effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AXI_SWITCH_SET</name>
+                  <description>Sets the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>POWERQUAD</name>
+              <description>POWERQUAD reset set</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>POWERQUAD_CLR</name>
+                  <description>No Effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>POWERQUAD_SET</name>
+                  <description>Sets the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CASPER</name>
+              <description>CASPER reset set</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>CASPER_CLR</name>
+                  <description>No Effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CASPER_SET</name>
+                  <description>Sets the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>HASHCRYPT</name>
+              <description>HASHCRYPT reset set</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>HASHCRYPT_CLR</name>
+                  <description>No Effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HASHCRYPT_SET</name>
+                  <description>Sets the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PUF</name>
+              <description>PUF reset set</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PUF_CLR</name>
+                  <description>No Effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PUF_SET</name>
+                  <description>Sets the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RNG</name>
+              <description>RNG reset set</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>RNG_CLR</name>
+                  <description>No Effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RNG_SET</name>
+                  <description>Sets the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FLEXSPI0_OTFAD</name>
+              <description>FLEXSPI0 and OTFAD reset set</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>FLEXSPI0_OTFAD_CLR</name>
+                  <description>No Effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FLEXSPI0_OTFAD_SET</name>
+                  <description>Sets the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FLEXSPI1</name>
+              <description>FLEXSPI1 reset set</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>FLEXSPI1_CLR</name>
+                  <description>No Effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FLEXSPI1_SET</name>
+                  <description>Sets the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>USBHS_PHY</name>
+              <description>USB PHY reset set</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>USBHS_PHY_CLR</name>
+                  <description>No Effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USBHS_PHY_SET</name>
+                  <description>Sets the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>USBHS_DEVICE</name>
+              <description>USB Device reset set</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>USBHS_DEVICE_CLR</name>
+                  <description>No Effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USBHS_DEVICE_SET</name>
+                  <description>Sets the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>USBHS_HOST</name>
+              <description>USB HOST reset set</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>USBHS_HOST_CLR</name>
+                  <description>No Effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USBHS_HOST_SET</name>
+                  <description>Sets the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>USBHS_SRAM</name>
+              <description>USBHS SRAM reset set</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>USBHS_SRAM_CLR</name>
+                  <description>No Effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USBHS_SRAM_SET</name>
+                  <description>Sets the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SCT</name>
+              <description>SCTimer reset set</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>SCT_CLR</name>
+                  <description>No Effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCT_SET</name>
+                  <description>Sets the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GPU</name>
+              <description>GPU reset set</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>GPU_CLR</name>
+                  <description>No Effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPU_SET</name>
+                  <description>Sets the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DISPLAY_CONTROLLER</name>
+              <description>LCDIF DISPLAY CONTROLLER reset set</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>DISPLAY_CONTROLLER_CLR</name>
+                  <description>No Effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DISPLAY_CONTROLLER_SET</name>
+                  <description>Sets the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MIPI_DSI_CONTROLLER</name>
+              <description>MIPI DSI controller reset set</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>MIPI_DSI_CONTROLLER_CLR</name>
+                  <description>No Effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MIPI_DSI_CONTROLLER_SET</name>
+                  <description>Sets the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MIPI_DSI_PHY</name>
+              <description>MIPI DSI PHY reset set</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>MIPI_DSI_PHY_CLR</name>
+                  <description>No Effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MIPI_DSI_PHY_SET</name>
+                  <description>Sets the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SMARTDMA</name>
+              <description>SMARTDMA Event/Algorithm handler reset set</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>SMARTDMA_CLR</name>
+                  <description>No Effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SMARTDMA_SET</name>
+                  <description>Sets the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRSTCTL1_SET</name>
+          <description>Peripheral Reset Control Register 1 SET</description>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>SDIO0</name>
+              <description>SDIO0 reset set</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>SDIO0_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SDIO0_SET</name>
+                  <description>Sets the PRSTCTL1 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SDIO1</name>
+              <description>SDIO1 reset set</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>SDIO1_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SDIO1_SET</name>
+                  <description>Sets the PRSTCTL1 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ACMP0</name>
+              <description>ACMP0 reset set</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>ACMP0_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ACMP0_SET</name>
+                  <description>Sets the PRSTCTL1 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADC0</name>
+              <description>ADC0 reset set</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>ADC0_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ADC0_SET</name>
+                  <description>Sets the PRSTCTL1 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SHSGPIO0</name>
+              <description>SHSGPIO0 reset set</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>SHSGPIO0_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SHSGPIO0_SET</name>
+                  <description>Sets the PRSTCTL1 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRSTCTL2_SET</name>
+          <description>Peripheral Reset Control Register 2 SET</description>
+          <addressOffset>0x48</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>UTICK0</name>
+              <description>Micro-tick timer 0 reset set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>UTICK0_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UTICK0_SET</name>
+                  <description>Sets the PRSTCTL2 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WWDT0</name>
+              <description>WWDT0 reset set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>WWDT0_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WWDT0_SET</name>
+                  <description>Sets the PRSTCTL2 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRSTCTL0_CLR</name>
+          <description>Peripheral Reset Control Register 0 CLR</description>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>DSP</name>
+              <description>Fusion_ F1 DSP reset clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>DSP_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSP_SET</name>
+                  <description>Clears the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AXI_SWITCH</name>
+              <description>AXI SWITCH reset clear</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>AXI_SWITCH_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AXI_SWITCH_SET</name>
+                  <description>Clears the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>POWERQUAD</name>
+              <description>POWERQUAD reset clear</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>POWERQUAD_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>POWERQUAD_SET</name>
+                  <description>Clears the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CASPER</name>
+              <description>CASPER reset clear</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>CASPER_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CASPER_SET</name>
+                  <description>Clears the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>HASHCRYPT</name>
+              <description>HASHCRYPT reset clear</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>HASHCRYPT_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HASHCRYPT_SET</name>
+                  <description>Clears the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PUF</name>
+              <description>PUF reset clear</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PUF_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PUF_SET</name>
+                  <description>Clears the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RNG</name>
+              <description>RNG reset clear</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>RNG_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RNG_SET</name>
+                  <description>Clears the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FLEXSPI0_OTFAD</name>
+              <description>FLEXSPI0 and OTFAD reset clear</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>FLEXSPI0_OTFAD_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FLEXSPI0_OTFAD_SET</name>
+                  <description>Clears the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FLEXSPI1</name>
+              <description>FLEXSPI1 reset clear</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>FLEXSPI1_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FLEXSPI1_SET</name>
+                  <description>Clears the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>USBHS_PHY</name>
+              <description>USB PHY reset clear</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>USBHS_PHY_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USBHS_PHY_SET</name>
+                  <description>Clears the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>USBHS_DEVICE</name>
+              <description>USB DEVICE reset clear</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>USBHS_DEVICE_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USBHS_DEVICE_SET</name>
+                  <description>Clears the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>USBHS_HOST</name>
+              <description>USB HOST reset clear</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>USBHS_HOST_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USBHS_HOST_SET</name>
+                  <description>Clears the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>USBHS_SRAM</name>
+              <description>USBHS SRAM reset clear</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>USBHS_SRAM_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USBHS_SRAM_SET</name>
+                  <description>Clears the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SCT</name>
+              <description>SCT reset clear</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>SCT_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCT_SET</name>
+                  <description>Clears the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GPU</name>
+              <description>GPU reset clear</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>GPU_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPU_SET</name>
+                  <description>Clears the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DISPLAY_CONTROLLER</name>
+              <description>LCDIF DISPLAY CONTROLLER reset clear</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>DISPLAY_CONTROLLER_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DISPLAY_CONTROLLER_SET</name>
+                  <description>Clears the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MIPI_DSI_CONTROLLER</name>
+              <description>MIPI DSI controller reset clear</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>MIPI_DSI_CONTROLLER_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MIPI_DSI_CONTROLLER_SET</name>
+                  <description>Clears the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MIPI_DSI_PHY</name>
+              <description>MIPI DSI PHY reset clear</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>MIPI_DSI_PHY_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MIPI_DSI_PHY_SET</name>
+                  <description>Clears the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SMARTDMA</name>
+              <description>SMARTDMA Event/Algorithm handler reset clear</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>SMARTDMA_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SMARTDMA_SET</name>
+                  <description>Clears the PRSTCTL0 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRSTCTL1_CLR</name>
+          <description>Peripheral Reset Control Register 1 CLR</description>
+          <addressOffset>0x74</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>SDIO0</name>
+              <description>SDIO0 reset clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>SDIO0_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SDIO0_SET</name>
+                  <description>Clears the PRSTCTL1 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SDIO1</name>
+              <description>SDIO1 reset clear</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>SDIO1_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SDIO1_SET</name>
+                  <description>Clears the PRSTCTL1 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ACMP0</name>
+              <description>ACMP0 reset clear</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>ACMP0_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ACMP0_SET</name>
+                  <description>Clears the PRSTCTL1 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADC0</name>
+              <description>ADC0 reset clear</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>ADC0_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ADC0_SET</name>
+                  <description>Clears the PRSTCTL1 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SHSGPIO0</name>
+              <description>Secure HSGPIO0 reset clear</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>SHSGPIO0_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SHSGPIO0_SET</name>
+                  <description>Clears the PRSTCTL1 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRSTCTL2_CLR</name>
+          <description>Peripheral Reset Control Register 2 CLR</description>
+          <addressOffset>0x78</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>UTICK0</name>
+              <description>Micro-tick timer 0 reset clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>UTICK0_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UTICK0_SET</name>
+                  <description>Clears the PRSTCTL2 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WWDT0</name>
+              <description>WWDT0 reset clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>WWDT0_CLR</name>
+                  <description>No effect</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WWDT0_SET</name>
+                  <description>Clears the PRSTCTL2 Bit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+  </peripherals>
+</device>
\ No newline at end of file