| Message ID | 20240804-clk-u64-v4-2-8e55569f39a4@nxp.com (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Headers | show |
| Series | clk: add assigned-clock-rates-u64 | expand |
Quoting Peng Fan (OSS) (2024-08-04 05:32:56) > From: Peng Fan <peng.fan@nxp.com> > > i.MX95 System Management Control Firmware(SCMI) manages the clock > function, it exposes PLL VCO which could support up to 5GHz rate that > exceeds UINT32_MAX. So add assigned-clock-rates-u64 support > to set rate that exceeds UINT32_MAX. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- > drivers/clk/clk-conf.c | 42 +++++++++++++++++++++++++++++++++++++----- > 1 file changed, 37 insertions(+), 5 deletions(-) Thanks. I'd like to have a DT overlay KUnit test for this as well. Either you can write it, or I'll write it next week.
Hi Stephen, > Subject: Re: [PATCH v4 2/2] clk: clk-conf: support assigned-clock-rates- > u64 > > Quoting Peng Fan (OSS) (2024-08-04 05:32:56) > > From: Peng Fan <peng.fan@nxp.com> > > > > i.MX95 System Management Control Firmware(SCMI) manages the > clock > > function, it exposes PLL VCO which could support up to 5GHz rate > that > > exceeds UINT32_MAX. So add assigned-clock-rates-u64 support to > set > > rate that exceeds UINT32_MAX. > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > > --- > > drivers/clk/clk-conf.c | 42 > > +++++++++++++++++++++++++++++++++++++----- > > 1 file changed, 37 insertions(+), 5 deletions(-) > > Thanks. I'd like to have a DT overlay KUnit test for this as well. > Either you can write it, or I'll write it next week. I am new in writing KUnit test. If you would do that, that is Great. Thanks in advance. Thanks, Peng.
Quoting Peng Fan (OSS) (2024-08-04 05:32:56) > From: Peng Fan <peng.fan@nxp.com> > > i.MX95 System Management Control Firmware(SCMI) manages the clock > function, it exposes PLL VCO which could support up to 5GHz rate that > exceeds UINT32_MAX. So add assigned-clock-rates-u64 support > to set rate that exceeds UINT32_MAX. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- The patch doesn't compile because of missing slab.h include. I added it and applied to clk-next.
> Subject: Re: [PATCH v4 2/2] clk: clk-conf: support assigned-clock-rates- > u64 > > Quoting Peng Fan (OSS) (2024-08-04 05:32:56) > > From: Peng Fan <peng.fan@nxp.com> > > > > i.MX95 System Management Control Firmware(SCMI) manages the > clock > > function, it exposes PLL VCO which could support up to 5GHz rate > that > > exceeds UINT32_MAX. So add assigned-clock-rates-u64 support to > set > > rate that exceeds UINT32_MAX. > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > > --- > > The patch doesn't compile because of missing slab.h include. I added it > and applied to clk-next. I did not meet build issue for ARM64, but anyway thanks for helping handle it. Thanks, Peng.
diff --git a/drivers/clk/clk-conf.c b/drivers/clk/clk-conf.c index 058420562020..51f994366d73 100644 --- a/drivers/clk/clk-conf.c +++ b/drivers/clk/clk-conf.c @@ -81,11 +81,44 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier) static int __set_clk_rates(struct device_node *node, bool clk_supplier) { struct of_phandle_args clkspec; - int rc, index = 0; + int rc, count, count_64, index; struct clk *clk; - u32 rate; + u64 *rates_64 __free(kfree) = NULL; + u32 *rates __free(kfree) = NULL; + + count = of_property_count_u32_elems(node, "assigned-clock-rates"); + count_64 = of_property_count_u64_elems(node, "assigned-clock-rates-u64"); + if (count_64 > 0) { + count = count_64; + rates_64 = kcalloc(count, sizeof(*rates_64), GFP_KERNEL); + if (!rates_64) + return -ENOMEM; + + rc = of_property_read_u64_array(node, + "assigned-clock-rates-u64", + rates_64, count); + } else if (count > 0) { + rates = kcalloc(count, sizeof(*rates), GFP_KERNEL); + if (!rates) + return -ENOMEM; + + rc = of_property_read_u32_array(node, "assigned-clock-rates", + rates, count); + } else { + return 0; + } + + if (rc) + return rc; + + for (index = 0; index < count; index++) { + unsigned long rate; + + if (rates_64) + rate = rates_64[index]; + else + rate = rates[index]; - of_property_for_each_u32(node, "assigned-clock-rates", rate) { if (rate) { rc = of_parse_phandle_with_args(node, "assigned-clocks", "#clock-cells", index, &clkspec); @@ -112,12 +145,11 @@ static int __set_clk_rates(struct device_node *node, bool clk_supplier) rc = clk_set_rate(clk, rate); if (rc < 0) - pr_err("clk: couldn't set %s clk rate to %u (%d), current rate: %lu\n", + pr_err("clk: couldn't set %s clk rate to %lu (%d), current rate: %lu\n", __clk_get_name(clk), rate, rc, clk_get_rate(clk)); clk_put(clk); } - index++; } return 0; }