| Message ID | 20240814133928.6746-3-philmd@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | linux-user/mips: Select correct CPUs | expand |
On 8/14/24 23:39, Philippe Mathieu-Daudé wrote: > The Octeon68XX CPU is available since commit 9a6046a655 > ("target/mips: introduce Cavium Octeon CPU model"). > > Cc: Pavel Dovgalyuk<Pavel.Dovgalyuk@ispras.ru> > Resolves:https://gitlab.com/qemu-project/qemu/-/issues/1722 > Reported-by: Johnathan Hữu Trí<nhtri2003@gmail.com> > Suggested-by: Richard Henderson<richard.henderson@linaro.org> > Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org> > --- > linux-user/mips64/target_elf.h | 8 ++++++++ > 1 file changed, 8 insertions(+) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/linux-user/mips64/target_elf.h b/linux-user/mips64/target_elf.h index ec55d8542a..ce6fb6541e 100644 --- a/linux-user/mips64/target_elf.h +++ b/linux-user/mips64/target_elf.h @@ -9,6 +9,14 @@ #define MIPS64_TARGET_ELF_H static inline const char *cpu_get_model(uint32_t eflags) { + switch (eflags & EF_MIPS_MACH) { + case EF_MIPS_MACH_OCTEON: + case EF_MIPS_MACH_OCTEON2: + case EF_MIPS_MACH_OCTEON3: + return "Octeon68XX"; + default: + break; + } if ((eflags & EF_MIPS_ARCH) == EF_MIPS_ARCH_64R6) { return "I6400"; }
The Octeon68XX CPU is available since commit 9a6046a655 ("target/mips: introduce Cavium Octeon CPU model"). Cc: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1722 Reported-by: Johnathan Hữu Trí <nhtri2003@gmail.com> Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- linux-user/mips64/target_elf.h | 8 ++++++++ 1 file changed, 8 insertions(+)