| Message ID | 20240821070558.1020101-1-bbhushan2@marvell.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | af688a99eb1fc7ef69774665d61e6be51cea627a |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | [net,v3] octeontx2-af: Fix CPT AF register offset calculation | expand |
On Wed, Aug 21, 2024 at 12:35:58PM +0530, Bharat Bhushan wrote: > Some CPT AF registers are per LF and others are global. Translation > of PF/VF local LF slot number to actual LF slot number is required > only for accessing perf LF registers. CPT AF global registers access > do not require any LF slot number. Also, there is no reason CPT > PF/VF to know actual lf's register offset. > > Without this fix microcode loading will fail, VFs cannot be created > and hardware is not usable. > > Fixes: bc35e28af789 ("octeontx2-af: replace cpt slot with lf id on reg write") > Signed-off-by: Bharat Bhushan <bbhushan2@marvell.com> > --- > v3: > - Updated patch description about what's broken without this fix > - Added patch history > > v2: https://lore.kernel.org/netdev/20240819152744.GA543198@kernel.org/T/ > - Spelling fixes in patch description > > v1: https://lore.kernel.org/lkml/CAAeCc_nJtR2ryzoaXop8-bbw_0RGciZsniiUqS+NVMg7dHahiQ@mail.gmail.com/T/ > - Added "net" in patch subject prefix, missed in previous patch: > https://lore.kernel.org/lkml/20240806070239.1541623-1-bbhushan2@marvell.com/ > Thanks for the updates, and the information below the scissors ('---'). Reviewed-by: Simon Horman <horms@kernel.org>
Hello: This patch was applied to netdev/net.git (main) by Paolo Abeni <pabeni@redhat.com>: On Wed, 21 Aug 2024 12:35:58 +0530 you wrote: > Some CPT AF registers are per LF and others are global. Translation > of PF/VF local LF slot number to actual LF slot number is required > only for accessing perf LF registers. CPT AF global registers access > do not require any LF slot number. Also, there is no reason CPT > PF/VF to know actual lf's register offset. > > Without this fix microcode loading will fail, VFs cannot be created > and hardware is not usable. > > [...] Here is the summary with links: - [net,v3] octeontx2-af: Fix CPT AF register offset calculation https://git.kernel.org/netdev/net/c/af688a99eb1f You are awesome, thank you!
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c index 3e09d2285814..daf4b951e905 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c @@ -632,7 +632,9 @@ int rvu_mbox_handler_cpt_inline_ipsec_cfg(struct rvu *rvu, return ret; } -static bool is_valid_offset(struct rvu *rvu, struct cpt_rd_wr_reg_msg *req) +static bool validate_and_update_reg_offset(struct rvu *rvu, + struct cpt_rd_wr_reg_msg *req, + u64 *reg_offset) { u64 offset = req->reg_offset; int blkaddr, num_lfs, lf; @@ -663,6 +665,11 @@ static bool is_valid_offset(struct rvu *rvu, struct cpt_rd_wr_reg_msg *req) if (lf < 0) return false; + /* Translate local LF's offset to global CPT LF's offset to + * access LFX register. + */ + *reg_offset = (req->reg_offset & 0xFF000) + (lf << 3); + return true; } else if (!(req->hdr.pcifunc & RVU_PFVF_FUNC_MASK)) { /* Registers that can be accessed from PF */ @@ -697,7 +704,7 @@ int rvu_mbox_handler_cpt_rd_wr_register(struct rvu *rvu, struct cpt_rd_wr_reg_msg *rsp) { u64 offset = req->reg_offset; - int blkaddr, lf; + int blkaddr; blkaddr = validate_and_get_cpt_blkaddr(req->blkaddr); if (blkaddr < 0) @@ -708,18 +715,10 @@ int rvu_mbox_handler_cpt_rd_wr_register(struct rvu *rvu, !is_cpt_vf(rvu, req->hdr.pcifunc)) return CPT_AF_ERR_ACCESS_DENIED; - if (!is_valid_offset(rvu, req)) + if (!validate_and_update_reg_offset(rvu, req, &offset)) return CPT_AF_ERR_ACCESS_DENIED; - /* Translate local LF used by VFs to global CPT LF */ - lf = rvu_get_lf(rvu, &rvu->hw->block[blkaddr], req->hdr.pcifunc, - (offset & 0xFFF) >> 3); - - /* Translate local LF's offset to global CPT LF's offset */ - offset &= 0xFF000; - offset += lf << 3; - - rsp->reg_offset = offset; + rsp->reg_offset = req->reg_offset; rsp->ret_val = req->ret_val; rsp->is_write = req->is_write;
Some CPT AF registers are per LF and others are global. Translation of PF/VF local LF slot number to actual LF slot number is required only for accessing perf LF registers. CPT AF global registers access do not require any LF slot number. Also, there is no reason CPT PF/VF to know actual lf's register offset. Without this fix microcode loading will fail, VFs cannot be created and hardware is not usable. Fixes: bc35e28af789 ("octeontx2-af: replace cpt slot with lf id on reg write") Signed-off-by: Bharat Bhushan <bbhushan2@marvell.com> --- v3: - Updated patch description about what's broken without this fix - Added patch history v2: https://lore.kernel.org/netdev/20240819152744.GA543198@kernel.org/T/ - Spelling fixes in patch description v1: https://lore.kernel.org/lkml/CAAeCc_nJtR2ryzoaXop8-bbw_0RGciZsniiUqS+NVMg7dHahiQ@mail.gmail.com/T/ - Added "net" in patch subject prefix, missed in previous patch: https://lore.kernel.org/lkml/20240806070239.1541623-1-bbhushan2@marvell.com/ .../ethernet/marvell/octeontx2/af/rvu_cpt.c | 23 +++++++++---------- 1 file changed, 11 insertions(+), 12 deletions(-)