| Message ID | 20240815-preemption-a750-t-v1-6-7bda26c34037@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Preemption support for A7XX | expand |
On Thu, Aug 15, 2024 at 08:26:16PM +0200, Antonino Maniscalco wrote: > Some userspace changes are necessary so add a flag for userspace to > advertise support for preemption. So the intention is to fallback to level 0 preemption until user moves to Mesa libs with level 1 support for each new GPU? Please elaborate a bit. -Akhil. > > Signed-off-by: Antonino Maniscalco <antomani103@gmail.com> > --- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 ++++++++---- > include/uapi/drm/msm_drm.h | 5 ++++- > 2 files changed, 12 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index 1a90db5759b8..86357016db8d 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -453,8 +453,10 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) > OUT_PKT7(ring, CP_SET_MARKER, 1); > OUT_RING(ring, 0x101); /* IFPC disable */ > > - OUT_PKT7(ring, CP_SET_MARKER, 1); > - OUT_RING(ring, 0x00d); /* IB1LIST start */ > + if (submit->queue->flags & MSM_SUBMITQUEUE_ALLOW_PREEMPT) { > + OUT_PKT7(ring, CP_SET_MARKER, 1); > + OUT_RING(ring, 0x00d); /* IB1LIST start */ > + } > > /* Submit the commands */ > for (i = 0; i < submit->nr_cmds; i++) { > @@ -485,8 +487,10 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) > update_shadow_rptr(gpu, ring); > } > > - OUT_PKT7(ring, CP_SET_MARKER, 1); > - OUT_RING(ring, 0x00e); /* IB1LIST end */ > + if (submit->queue->flags & MSM_SUBMITQUEUE_ALLOW_PREEMPT) { > + OUT_PKT7(ring, CP_SET_MARKER, 1); > + OUT_RING(ring, 0x00e); /* IB1LIST end */ > + } > > get_stats_counter(ring, REG_A7XX_RBBM_PERFCTR_CP(0), > rbmemptr_stats(ring, index, cpcycles_end)); > diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h > index 3fca72f73861..f37858db34e6 100644 > --- a/include/uapi/drm/msm_drm.h > +++ b/include/uapi/drm/msm_drm.h > @@ -345,7 +345,10 @@ struct drm_msm_gem_madvise { > * backwards compatibility as a "default" submitqueue > */ > > -#define MSM_SUBMITQUEUE_FLAGS (0) > +#define MSM_SUBMITQUEUE_ALLOW_PREEMPT 0x00000001 > +#define MSM_SUBMITQUEUE_FLAGS ( \ > + MSM_SUBMITQUEUE_ALLOW_PREEMPT | \ > + 0) > > /* > * The submitqueue priority should be between 0 and MSM_PARAM_PRIORITIES-1, > > -- > 2.46.0 > >
On 15.08.2024 8:26 PM, Antonino Maniscalco wrote: > Some userspace changes are necessary so add a flag for userspace to > advertise support for preemption. > > Signed-off-by: Antonino Maniscalco <antomani103@gmail.com> > --- Squash this into the "add preemption" patch, or add the flag earlier (probably the latter, as that one is already big enough) As it stands, just applying patches 1..5 will break GPU IIUC.. and that's no bueno for running git bisect Konrad
On 20.08.2024 12:16 PM, Konrad Dybcio wrote: > On 15.08.2024 8:26 PM, Antonino Maniscalco wrote: >> Some userspace changes are necessary so add a flag for userspace to >> advertise support for preemption. >> >> Signed-off-by: Antonino Maniscalco <antomani103@gmail.com> >> --- > > Squash this into the "add preemption" patch, or add the flag earlier > (probably the latter, as that one is already big enough) > > As it stands, just applying patches 1..5 will break GPU IIUC.. and > that's no bueno for running git bisect Or not, since the ring number isn't increased until the next one.. Konrad
On Mon, Aug 19, 2024 at 9:31 PM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote: > > On Thu, Aug 15, 2024 at 08:26:16PM +0200, Antonino Maniscalco wrote: > > Some userspace changes are necessary so add a flag for userspace to > > advertise support for preemption. > > So the intention is to fallback to level 0 preemption until user moves > to Mesa libs with level 1 support for each new GPU? Please elaborate a bit. > > -Akhil. Yes, that's right. My Mesa series fixes L1 preemption and skipsaverestore by changing some of the CP_SET_MARKER calls and register programming and introducing CP_SET_AMBLE calls and then enables the flag on a7xx. Connor > > > > > Signed-off-by: Antonino Maniscalco <antomani103@gmail.com> > > --- > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 ++++++++---- > > include/uapi/drm/msm_drm.h | 5 ++++- > > 2 files changed, 12 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > index 1a90db5759b8..86357016db8d 100644 > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > @@ -453,8 +453,10 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) > > OUT_PKT7(ring, CP_SET_MARKER, 1); > > OUT_RING(ring, 0x101); /* IFPC disable */ > > > > - OUT_PKT7(ring, CP_SET_MARKER, 1); > > - OUT_RING(ring, 0x00d); /* IB1LIST start */ > > + if (submit->queue->flags & MSM_SUBMITQUEUE_ALLOW_PREEMPT) { > > + OUT_PKT7(ring, CP_SET_MARKER, 1); > > + OUT_RING(ring, 0x00d); /* IB1LIST start */ > > + } > > > > /* Submit the commands */ > > for (i = 0; i < submit->nr_cmds; i++) { > > @@ -485,8 +487,10 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) > > update_shadow_rptr(gpu, ring); > > } > > > > - OUT_PKT7(ring, CP_SET_MARKER, 1); > > - OUT_RING(ring, 0x00e); /* IB1LIST end */ > > + if (submit->queue->flags & MSM_SUBMITQUEUE_ALLOW_PREEMPT) { > > + OUT_PKT7(ring, CP_SET_MARKER, 1); > > + OUT_RING(ring, 0x00e); /* IB1LIST end */ > > + } > > > > get_stats_counter(ring, REG_A7XX_RBBM_PERFCTR_CP(0), > > rbmemptr_stats(ring, index, cpcycles_end)); > > diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h > > index 3fca72f73861..f37858db34e6 100644 > > --- a/include/uapi/drm/msm_drm.h > > +++ b/include/uapi/drm/msm_drm.h > > @@ -345,7 +345,10 @@ struct drm_msm_gem_madvise { > > * backwards compatibility as a "default" submitqueue > > */ > > > > -#define MSM_SUBMITQUEUE_FLAGS (0) > > +#define MSM_SUBMITQUEUE_ALLOW_PREEMPT 0x00000001 > > +#define MSM_SUBMITQUEUE_FLAGS ( \ > > + MSM_SUBMITQUEUE_ALLOW_PREEMPT | \ > > + 0) > > > > /* > > * The submitqueue priority should be between 0 and MSM_PARAM_PRIORITIES-1, > > > > -- > > 2.46.0 > > > >
On Tue, Aug 20, 2024 at 11:48:33AM +0100, Connor Abbott wrote: > On Mon, Aug 19, 2024 at 9:31 PM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote: > > > > On Thu, Aug 15, 2024 at 08:26:16PM +0200, Antonino Maniscalco wrote: > > > Some userspace changes are necessary so add a flag for userspace to > > > advertise support for preemption. > > > > So the intention is to fallback to level 0 preemption until user moves > > to Mesa libs with level 1 support for each new GPU? Please elaborate a bit. > > > > -Akhil. > > Yes, that's right. My Mesa series fixes L1 preemption and > skipsaverestore by changing some of the CP_SET_MARKER calls and > register programming and introducing CP_SET_AMBLE calls and then > enables the flag on a7xx. And we want to control L1 preemption per submitqueue because both freedreno and turnip may not have support ready at the same time? Antonino, since this is a UAPI update, it is good to have these details captured in the commit msg for reference. -Akhil. > > Connor > > > > > > > > > Signed-off-by: Antonino Maniscalco <antomani103@gmail.com> > > > --- > > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 ++++++++---- > > > include/uapi/drm/msm_drm.h | 5 ++++- > > > 2 files changed, 12 insertions(+), 5 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > > index 1a90db5759b8..86357016db8d 100644 > > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > > @@ -453,8 +453,10 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) > > > OUT_PKT7(ring, CP_SET_MARKER, 1); > > > OUT_RING(ring, 0x101); /* IFPC disable */ > > > > > > - OUT_PKT7(ring, CP_SET_MARKER, 1); > > > - OUT_RING(ring, 0x00d); /* IB1LIST start */ > > > + if (submit->queue->flags & MSM_SUBMITQUEUE_ALLOW_PREEMPT) { > > > + OUT_PKT7(ring, CP_SET_MARKER, 1); > > > + OUT_RING(ring, 0x00d); /* IB1LIST start */ > > > + } > > > > > > /* Submit the commands */ > > > for (i = 0; i < submit->nr_cmds; i++) { > > > @@ -485,8 +487,10 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) > > > update_shadow_rptr(gpu, ring); > > > } > > > > > > - OUT_PKT7(ring, CP_SET_MARKER, 1); > > > - OUT_RING(ring, 0x00e); /* IB1LIST end */ > > > + if (submit->queue->flags & MSM_SUBMITQUEUE_ALLOW_PREEMPT) { > > > + OUT_PKT7(ring, CP_SET_MARKER, 1); > > > + OUT_RING(ring, 0x00e); /* IB1LIST end */ > > > + } > > > > > > get_stats_counter(ring, REG_A7XX_RBBM_PERFCTR_CP(0), > > > rbmemptr_stats(ring, index, cpcycles_end)); > > > diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h > > > index 3fca72f73861..f37858db34e6 100644 > > > --- a/include/uapi/drm/msm_drm.h > > > +++ b/include/uapi/drm/msm_drm.h > > > @@ -345,7 +345,10 @@ struct drm_msm_gem_madvise { > > > * backwards compatibility as a "default" submitqueue > > > */ > > > > > > -#define MSM_SUBMITQUEUE_FLAGS (0) > > > +#define MSM_SUBMITQUEUE_ALLOW_PREEMPT 0x00000001 > > > +#define MSM_SUBMITQUEUE_FLAGS ( \ > > > + MSM_SUBMITQUEUE_ALLOW_PREEMPT | \ > > > + 0) > > > > > > /* > > > * The submitqueue priority should be between 0 and MSM_PARAM_PRIORITIES-1, > > > > > > -- > > > 2.46.0 > > > > > >
On 8/22/24 9:21 PM, Akhil P Oommen wrote: > On Tue, Aug 20, 2024 at 11:48:33AM +0100, Connor Abbott wrote: >> On Mon, Aug 19, 2024 at 9:31 PM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote: >>> >>> On Thu, Aug 15, 2024 at 08:26:16PM +0200, Antonino Maniscalco wrote: >>>> Some userspace changes are necessary so add a flag for userspace to >>>> advertise support for preemption. >>> >>> So the intention is to fallback to level 0 preemption until user moves >>> to Mesa libs with level 1 support for each new GPU? Please elaborate a bit. >>> >>> -Akhil. >> >> Yes, that's right. My Mesa series fixes L1 preemption and >> skipsaverestore by changing some of the CP_SET_MARKER calls and >> register programming and introducing CP_SET_AMBLE calls and then >> enables the flag on a7xx. > > And we want to control L1 preemption per submitqueue because both > freedreno and turnip may not have support ready at the same time? > > Antonino, since this is a UAPI update, it is good to have these details > captured in the commit msg for reference. > > -Akhil. > Sure I will update the commit message. Anyway that could be a valid reason but there is also nothing preventing you from loading different versions of mesa in two different processes so having one globally enable preemption and break it for the other wouldn't be ideal. It felt natural to have it per submitqueue. Best regards,
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 1a90db5759b8..86357016db8d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -453,8 +453,10 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) OUT_PKT7(ring, CP_SET_MARKER, 1); OUT_RING(ring, 0x101); /* IFPC disable */ - OUT_PKT7(ring, CP_SET_MARKER, 1); - OUT_RING(ring, 0x00d); /* IB1LIST start */ + if (submit->queue->flags & MSM_SUBMITQUEUE_ALLOW_PREEMPT) { + OUT_PKT7(ring, CP_SET_MARKER, 1); + OUT_RING(ring, 0x00d); /* IB1LIST start */ + } /* Submit the commands */ for (i = 0; i < submit->nr_cmds; i++) { @@ -485,8 +487,10 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) update_shadow_rptr(gpu, ring); } - OUT_PKT7(ring, CP_SET_MARKER, 1); - OUT_RING(ring, 0x00e); /* IB1LIST end */ + if (submit->queue->flags & MSM_SUBMITQUEUE_ALLOW_PREEMPT) { + OUT_PKT7(ring, CP_SET_MARKER, 1); + OUT_RING(ring, 0x00e); /* IB1LIST end */ + } get_stats_counter(ring, REG_A7XX_RBBM_PERFCTR_CP(0), rbmemptr_stats(ring, index, cpcycles_end)); diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h index 3fca72f73861..f37858db34e6 100644 --- a/include/uapi/drm/msm_drm.h +++ b/include/uapi/drm/msm_drm.h @@ -345,7 +345,10 @@ struct drm_msm_gem_madvise { * backwards compatibility as a "default" submitqueue */ -#define MSM_SUBMITQUEUE_FLAGS (0) +#define MSM_SUBMITQUEUE_ALLOW_PREEMPT 0x00000001 +#define MSM_SUBMITQUEUE_FLAGS ( \ + MSM_SUBMITQUEUE_ALLOW_PREEMPT | \ + 0) /* * The submitqueue priority should be between 0 and MSM_PARAM_PRIORITIES-1,
Some userspace changes are necessary so add a flag for userspace to advertise support for preemption. Signed-off-by: Antonino Maniscalco <antomani103@gmail.com> --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 ++++++++---- include/uapi/drm/msm_drm.h | 5 ++++- 2 files changed, 12 insertions(+), 5 deletions(-)