| Message ID | 20240822-friendlyelec-nanopc-t6-lts-v4-1-892aebcec0c6@linaro.org (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | FriendlyELEC NanoPC-T6 improvements | expand |
Hi Marcin, On 2024-08-22 15:32, Marcin Juszkiewicz wrote: > There are definitions for M0 and M2 pinouts while NanoPC-T6 uses M1 one. > > Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> > --- > arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi > index 30db12c4fc82..75d5816b6fa4 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi > @@ -407,6 +407,23 @@ fspim0_cs1: fspim0-cs1 { > <2 RK_PD7 2 &pcfg_pull_up_drv_level_2>; > }; > > + /omit-if-no-ref/ > + fspim1_pins: fspim1-pins { > + rockchip,pins = > + /* fspi_clk_m1 */ > + <2 RK_PB3 5 &pcfg_pull_up_drv_level_2>, > + /* fspi_cs0n_m1 */ > + <2 RK_PB4 2 &pcfg_pull_up_drv_level_2>, > + /* fspi_d0_m1 */ > + <2 RK_PA6 5 &pcfg_pull_up_drv_level_2>, > + /* fspi_d1_m1 */ > + <2 RK_PA7 5 &pcfg_pull_up_drv_level_2>, > + /* fspi_d2_m1 */ > + <2 RK_PB0 5 &pcfg_pull_up_drv_level_2>, > + /* fspi_d3_m1 */ > + <2 RK_PB1 5 &pcfg_pull_up_drv_level_2>; > + }; fspim1_pins already exists in rk3588-extra-pinctrl.dtsi, also look like this uses wrong function 5 instead of function 3. Because rk3588-extra-pinctrl is included after rk3588-base-pinctrl the function is corrected and this patch has no real effect. Please drop this patch. Regards, Jonas > + > /omit-if-no-ref/ > fspim2_pins: fspim2-pins { > rockchip,pins = >
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi index 30db12c4fc82..75d5816b6fa4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi @@ -407,6 +407,23 @@ fspim0_cs1: fspim0-cs1 { <2 RK_PD7 2 &pcfg_pull_up_drv_level_2>; }; + /omit-if-no-ref/ + fspim1_pins: fspim1-pins { + rockchip,pins = + /* fspi_clk_m1 */ + <2 RK_PB3 5 &pcfg_pull_up_drv_level_2>, + /* fspi_cs0n_m1 */ + <2 RK_PB4 2 &pcfg_pull_up_drv_level_2>, + /* fspi_d0_m1 */ + <2 RK_PA6 5 &pcfg_pull_up_drv_level_2>, + /* fspi_d1_m1 */ + <2 RK_PA7 5 &pcfg_pull_up_drv_level_2>, + /* fspi_d2_m1 */ + <2 RK_PB0 5 &pcfg_pull_up_drv_level_2>, + /* fspi_d3_m1 */ + <2 RK_PB1 5 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ fspim2_pins: fspim2-pins { rockchip,pins =
There are definitions for M0 and M2 pinouts while NanoPC-T6 uses M1 one. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> --- arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)