Message ID | 20240805131709.101679-2-biju.das.jz@bp.renesas.com (mailing list archive) |
---|---|
State | Mainlined |
Commit | a94a244a5b1a2040611aaaa17fd23dd908bc01ac |
Delegated to: | Geert Uytterhoeven |
Headers | show |
Series | Add RZ/G2UL {fcpvd, vspd} device nodes | expand |
On Mon, Aug 5, 2024 at 3:17 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > Add fcpvd node to RZ/G2UL SoC DTSI. > > Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > v2->v3: > * Reordered the patch as vspd needs fcpvd handle, so added fcpvd node > first > * Added Rb tag from Laurent. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v6.12. Gr{oetje,eeting}s, Geert
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi index 18ef297db933..c4defdf0fefd 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi @@ -129,6 +129,17 @@ csi2cru: endpoint@0 { }; }; + fcpvd: fcp@10880000 { + compatible = "renesas,r9a07g043u-fcpvd", "renesas,fcpv"; + reg = <0 0x10880000 0 0x10000>; + clocks = <&cpg CPG_MOD R9A07G043_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G043_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G043_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_LCDC_RESET_N>; + }; + irqc: interrupt-controller@110a0000 { compatible = "renesas,r9a07g043u-irqc", "renesas,rzg2l-irqc";