| Message ID | 20240714141315.19480-1-claudiu.beznea@tuxon.dev (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | clk: at91: sama7g5: Allocate only the needed amount of memory for PLLs | expand |
Quoting Claudiu Beznea (2024-07-14 07:13:15) > The maximum number of PLL components on SAMA7G5 is 3 (one fractional > part and 2 dividers). Allocate the needed amount of memory for > sama7g5_plls 2d array. Previous code used to allocate 7 array entries for > each PLL. While at it, replace 3 with PLL_COMPID_MAX in the loop which > parses the sama7g5_plls 2d array. > > Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> > --- Might as well add a Fixes tag so we know when it was less efficient and to help anyone trying to backport this driver. Acked-by: Stephen Boyd <sboyd@kernel.org>
On 15.07.2024 22:47, Stephen Boyd wrote: > Quoting Claudiu Beznea (2024-07-14 07:13:15) >> The maximum number of PLL components on SAMA7G5 is 3 (one fractional >> part and 2 dividers). Allocate the needed amount of memory for >> sama7g5_plls 2d array. Previous code used to allocate 7 array entries for >> each PLL. While at it, replace 3 with PLL_COMPID_MAX in the loop which >> parses the sama7g5_plls 2d array. >> >> Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> >> --- > > Might as well add a Fixes tag so we know when it was less efficient and > to help anyone trying to backport this driver. That would be: Fixes: cb783bbbcf54 ("clk: at91: sama7g5: add clock support for sama7g5") Thank you, Claudiu Beznea > > Acked-by: Stephen Boyd <sboyd@kernel.org>
On 14.07.2024 17:13, Claudiu Beznea wrote: > The maximum number of PLL components on SAMA7G5 is 3 (one fractional > part and 2 dividers). Allocate the needed amount of memory for > sama7g5_plls 2d array. Previous code used to allocate 7 array entries for > each PLL. While at it, replace 3 with PLL_COMPID_MAX in the loop which > parses the sama7g5_plls 2d array. > > Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Applied to clk-microchip, thanks!
diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 6706d1305baa..8385badc1c70 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -51,6 +51,7 @@ enum pll_component_id { PLL_COMPID_FRAC, PLL_COMPID_DIV0, PLL_COMPID_DIV1, + PLL_COMPID_MAX, }; /* @@ -157,7 +158,7 @@ static struct sama7g5_pll { u8 t; u8 eid; u8 safe_div; -} sama7g5_plls[][PLL_ID_MAX] = { +} sama7g5_plls[][PLL_COMPID_MAX] = { [PLL_ID_CPU] = { [PLL_COMPID_FRAC] = { .n = "cpupll_fracck", @@ -1030,7 +1031,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np) sama7g5_pmc->chws[PMC_MAIN] = hw; for (i = 0; i < PLL_ID_MAX; i++) { - for (j = 0; j < 3; j++) { + for (j = 0; j < PLL_COMPID_MAX; j++) { struct clk_hw *parent_hw; if (!sama7g5_plls[i][j].n)
The maximum number of PLL components on SAMA7G5 is 3 (one fractional part and 2 dividers). Allocate the needed amount of memory for sama7g5_plls 2d array. Previous code used to allocate 7 array entries for each PLL. While at it, replace 3 with PLL_COMPID_MAX in the loop which parses the sama7g5_plls 2d array. Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> --- drivers/clk/at91/sama7g5.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)