diff mbox series

[v3,09/10] irqchip: irq-mips-cpu: Rework software IRQ handling flow

Message ID 20240810-b4-mips-ipi-improvements-v3-9-1224fd7c4096@flygoat.com (mailing list archive)
State Superseded
Headers show
Series MIPS: IPI Improvements | expand

Commit Message

Jiaxun Yang Aug. 10, 2024, 12:39 p.m. UTC 
Remove unnecessary irq_chip hooks for software interrupts,
and don't mask them in ack hook to match kernel's expectation
on handling flow.

Create a irq_chip for regular (non-MT) mode software interrupts
so they will be acked as well.

Tested-by: Serge Semin <fancer.lancer@gmail.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 drivers/irqchip/irq-mips-cpu.c | 57 +++++++++++++++++++++++++++++-------------
 1 file changed, 39 insertions(+), 18 deletions(-)

Comments

Thomas Gleixner Aug. 23, 2024, 7:37 p.m. UTC | #1 
On Sat, Aug 10 2024 at 13:39, Jiaxun Yang wrote:

Please fix the subsystem prefix.

> Remove unnecessary irq_chip hooks for software interrupts,
> and don't mask them in ack hook to match kernel's expectation
> on handling flow.

What's that expectation? You fail to explain why the current code is not
matching them.

> Create a irq_chip for regular (non-MT) mode software interrupts
> so they will be acked as well.

I'm failing to understand what this is about due to the lack of
information above.

> -static struct irq_chip mips_cpu_irq_controller = {
> +static unsigned int mips_sw_irq_startup(struct irq_data *d)
> +{
> +	clear_c0_cause(C_SW0 << d->hwirq);
> +	back_to_back_c0_hazard();
> +	unmask_mips_irq(d);
> +	return 0;
> +}
> +
> +static void mips_sw_irq_ack(struct irq_data *d)
> +{
> +	clear_c0_cause(C_SW0 << d->hwirq);
> +	back_to_back_c0_hazard();
> +}

Please move these functions to the place which actually requires them,
i.e. after the cpu controller struct and before the new one.

> +
> +static const struct irq_chip mips_cpu_irq_controller = {
>  	.name		= "MIPS",
>  	.irq_ack	= mask_mips_irq,
>  	.irq_mask	= mask_mips_irq,
> @@ -60,11 +74,19 @@ static struct irq_chip mips_cpu_irq_controller = {
>  	.irq_enable	= unmask_mips_irq,
>  };
>  
> +static const struct irq_chip mips_cpu_sw_irq_controller = {
> +	.name		= "MIPS",
> +	.irq_startup	= mips_sw_irq_startup,
> +	.irq_ack	= mips_sw_irq_ack,
> +	.irq_mask	= mask_mips_irq,
> +	.irq_unmask	= unmask_mips_irq,
> +};

  
>  asmlinkage void __weak plat_irq_dispatch(void)
>  {
> @@ -152,11 +170,14 @@ asmlinkage void __weak plat_irq_dispatch(void)
>  static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq,
>  			     irq_hw_number_t hw)
>  {
> -	struct irq_chip *chip;
> +	const struct irq_chip *chip;
>  
> -	if (hw < 2 && cpu_has_mipsmt) {
> -		/* Software interrupts are used for MT/CMT IPI */
> -		chip = &mips_mt_cpu_irq_controller;
> +	if (hw < 2) {
> +		chip = &mips_cpu_sw_irq_controller;
> +#ifdef CONFIG_MIPS_MT
> +		if (cpu_has_mipsmt)
> +			chip = &mips_mt_cpu_irq_controller;
> +#endif

Please move this into a helper function:

#ifdef CONFIG_MIPS_MT
static inline const struct irq_chip *mips_get_cpu_irqchip(void)
{
        return cpu_has_mipsmt ? &mips_mt_cpu_sw_irq_controller : &mips_cpu_sw_irq_controller;
}
#else
#define 
static inline const struct irq_chip *mips_get_cpu_irqchip(void)
{
        return &mips_cpu_sw_irq_controller;
}
#endif

Hmm?

Thanks,

        tglx
Jiaxun Yang Aug. 24, 2024, 9:52 a.m. UTC | #2 
在2024年8月23日八月 下午8:37，Thomas Gleixner写道：
> On Sat, Aug 10 2024 at 13:39, Jiaxun Yang wrote:
>
> Please fix the subsystem prefix.
>

Sorry, what do you ment by subsystem prefix?

Thanks
- Jiaxun
Thomas Gleixner Aug. 25, 2024, 12:17 a.m. UTC | #3 
On Sat, Aug 24 2024 at 10:52, Jiaxun Yang wrote:

> 在2024年8月23日八月 下午8:37，Thomas Gleixner写道：
>> On Sat, Aug 10 2024 at 13:39, Jiaxun Yang wrote:
>>
>> Please fix the subsystem prefix.
>>
>
> Sorry, what do you ment by subsystem prefix?

I gave you the answer in the previous reply, but here is a link to
documentation:

https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#patch-subject
diff mbox series

Patch

diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c
index 7b3501485d95..4854c06ce652 100644
--- a/drivers/irqchip/irq-mips-cpu.c
+++ b/drivers/irqchip/irq-mips-cpu.c
@@ -49,7 +49,21 @@  static inline void mask_mips_irq(struct irq_data *d)
 	irq_disable_hazard();
 }
 
-static struct irq_chip mips_cpu_irq_controller = {
+static unsigned int mips_sw_irq_startup(struct irq_data *d)
+{
+	clear_c0_cause(C_SW0 << d->hwirq);
+	back_to_back_c0_hazard();
+	unmask_mips_irq(d);
+	return 0;
+}
+
+static void mips_sw_irq_ack(struct irq_data *d)
+{
+	clear_c0_cause(C_SW0 << d->hwirq);
+	back_to_back_c0_hazard();
+}
+
+static const struct irq_chip mips_cpu_irq_controller = {
 	.name		= "MIPS",
 	.irq_ack	= mask_mips_irq,
 	.irq_mask	= mask_mips_irq,
@@ -60,11 +74,19 @@  static struct irq_chip mips_cpu_irq_controller = {
 	.irq_enable	= unmask_mips_irq,
 };
 
+static const struct irq_chip mips_cpu_sw_irq_controller = {
+	.name		= "MIPS",
+	.irq_startup	= mips_sw_irq_startup,
+	.irq_ack	= mips_sw_irq_ack,
+	.irq_mask	= mask_mips_irq,
+	.irq_unmask	= unmask_mips_irq,
+};
+
+#ifdef CONFIG_MIPS_MT
 /*
  * Basically the same as above but taking care of all the MT stuff
  */
-
-static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)
+static unsigned int mips_mt_sw_irq_startup(struct irq_data *d)
 {
 	unsigned int vpflags = dvpe();
 
@@ -76,14 +98,14 @@  static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)
 
 /*
  * While we ack the interrupt interrupts are disabled and thus we don't need
- * to deal with concurrency issues.  Same for mips_cpu_irq_end.
+ * to deal with concurrency issues.
  */
-static void mips_mt_cpu_irq_ack(struct irq_data *d)
+static void mips_mt_sw_irq_ack(struct irq_data *d)
 {
 	unsigned int vpflags = dvpe();
+
 	clear_c0_cause(C_SW0 << d->hwirq);
 	evpe(vpflags);
-	mask_mips_irq(d);
 }
 
 #ifdef CONFIG_GENERIC_IRQ_IPI
@@ -108,21 +130,17 @@  static void mips_mt_send_ipi(struct irq_data *d, unsigned int cpu)
 }
 
 #endif /* CONFIG_GENERIC_IRQ_IPI */
-
-static struct irq_chip mips_mt_cpu_irq_controller = {
+static const struct irq_chip mips_mt_cpu_irq_controller = {
 	.name		= "MIPS",
-	.irq_startup	= mips_mt_cpu_irq_startup,
-	.irq_ack	= mips_mt_cpu_irq_ack,
+	.irq_startup	= mips_mt_sw_irq_startup,
+	.irq_ack	= mips_mt_sw_irq_ack,
 	.irq_mask	= mask_mips_irq,
-	.irq_mask_ack	= mips_mt_cpu_irq_ack,
 	.irq_unmask	= unmask_mips_irq,
-	.irq_eoi	= unmask_mips_irq,
-	.irq_disable	= mask_mips_irq,
-	.irq_enable	= unmask_mips_irq,
 #ifdef CONFIG_GENERIC_IRQ_IPI
 	.ipi_send_single = mips_mt_send_ipi,
 #endif
 };
+#endif
 
 asmlinkage void __weak plat_irq_dispatch(void)
 {
@@ -152,11 +170,14 @@  asmlinkage void __weak plat_irq_dispatch(void)
 static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq,
 			     irq_hw_number_t hw)
 {
-	struct irq_chip *chip;
+	const struct irq_chip *chip;
 
-	if (hw < 2 && cpu_has_mipsmt) {
-		/* Software interrupts are used for MT/CMT IPI */
-		chip = &mips_mt_cpu_irq_controller;
+	if (hw < 2) {
+		chip = &mips_cpu_sw_irq_controller;
+#ifdef CONFIG_MIPS_MT
+		if (cpu_has_mipsmt)
+			chip = &mips_mt_cpu_irq_controller;
+#endif
 	} else {
 		chip = &mips_cpu_irq_controller;
 	}