| Message ID | 20240821085644.240009-3-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add support for Renesas RZ/V2H(P) SoC and GP-EVK platform | expand |
Hi Prabhakar, On Wed, Aug 21, 2024 at 10:56 AM Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Add initial DTS for RZ/V2H GP-EVK board, adding the below support: > - Memory > - Clock inputs > - PINCTRL > - SCIF > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Thanks for your patch! > --- /dev/null > +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts > @@ -0,0 +1,61 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +/* > + * Device Tree Source for the RZ/V2H GP-EVK board > + * > + * Copyright (C) 2024 Renesas Electronics Corp. > + */ > + > +/dts-v1/; > + > +#include "r9a09g057.dtsi" > + > +/ { > + model = "Renesas GP-EVK Board based on r9a09g057h44"; > + compatible = "renesas,gp-evk", "renesas,r9a09g057h44", "renesas,r9a09g057"; Board name/compatible (and thus file name) are still under discussion... The rest LGTM. Gr{oetje,eeting}s, Geert
Hi Geert, On Mon, Aug 26, 2024 at 1:07 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Wed, Aug 21, 2024 at 10:56 AM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Add initial DTS for RZ/V2H GP-EVK board, adding the below support: > > - Memory > > - Clock inputs > > - PINCTRL > > - SCIF > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Thanks for your patch! > > > --- /dev/null > > +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts > > @@ -0,0 +1,61 @@ > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +/* > > + * Device Tree Source for the RZ/V2H GP-EVK board > > + * > > + * Copyright (C) 2024 Renesas Electronics Corp. > > + */ > > + > > +/dts-v1/; > > + > > +#include "r9a09g057.dtsi" > > + > > +/ { > > + model = "Renesas GP-EVK Board based on r9a09g057h44"; > > + compatible = "renesas,gp-evk", "renesas,r9a09g057h44", "renesas,r9a09g057"; > > Board name/compatible (and thus file name) are still under discussion... > As discussed internally I'll update the board name/compatible to "renesas,rzv2h-evk" and rename r9a09g057h44-gp-evk.dts to r9a09g057h44-rzv2h-evk.dts. Cheers, Prabhakar
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index fbd214a1a638..b2249a2710aa 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -137,5 +137,7 @@ dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc.dtb dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb +dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-gp-evk.dtb + dtb-$(CONFIG_ARCH_RCAR_GEN3) += draak-ebisu-panel-aa104xd12.dtbo dtb-$(CONFIG_ARCH_RCAR_GEN3) += salvator-panel-aa104xd12.dtbo diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts new file mode 100644 index 000000000000..593c48181248 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/V2H GP-EVK board + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +/dts-v1/; + +#include "r9a09g057.dtsi" + +/ { + model = "Renesas GP-EVK Board based on r9a09g057h44"; + compatible = "renesas,gp-evk", "renesas,r9a09g057h44", "renesas,r9a09g057"; + + aliases { + serial0 = &scif; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x1 0xF8000000>; + }; + + memory@240000000 { + device_type = "memory"; + reg = <0x2 0x40000000 0x2 0x00000000>; + }; +}; + +&audio_extal_clk { + clock-frequency = <22579200>; +}; + +&pinctrl { + scif_pins: scif { + pins = "SCIF_TXD", "SCIF_RXD"; + renesas,output-impedance = <1>; + }; +}; + +&qextal_clk { + clock-frequency = <24000000>; +}; + +&rtxin_clk { + clock-frequency = <32768>; +}; + +&scif { + pinctrl-0 = <&scif_pins>; + pinctrl-names = "default"; + + status = "okay"; +};