| Message ID | 20240825121156.2498810-1-dnyaneshwar.bhadane@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] drm/i915/gt: Whitelist COMMON_SLICE_CHICKEN1 for UMD access. | expand |
On Sun, Aug 25, 2024 at 05:41:56PM +0530, Dnyaneshwar Bhadane wrote: > As part of the recommended tuning setting, whitelist COMMON_SLICE_CHICKEN1 > for MTL/ARL and DG2. > > The UMD will selectively enable or disable specific bits of the > register based on the type of workload and its requirements. > > v2: Remove the KMD par of enabling specific bits(Matt R) > > Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index bfe6d8fc820f..6aefbbcdd269 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -2072,7 +2072,7 @@ static void dg2_whitelist_build(struct intel_engine_cs *engine) > case RENDER_CLASS: > /* Required by recommended tuning setting (not a workaround) */ > whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3); > - > + whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); > break; > default: > break; > @@ -2087,7 +2087,7 @@ static void xelpg_whitelist_build(struct intel_engine_cs *engine) > case RENDER_CLASS: > /* Required by recommended tuning setting (not a workaround) */ > whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3); > - > + whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); > break; > default: > break; > -- > 2.34.1 >
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index bfe6d8fc820f..6aefbbcdd269 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2072,7 +2072,7 @@ static void dg2_whitelist_build(struct intel_engine_cs *engine) case RENDER_CLASS: /* Required by recommended tuning setting (not a workaround) */ whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3); - + whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); break; default: break; @@ -2087,7 +2087,7 @@ static void xelpg_whitelist_build(struct intel_engine_cs *engine) case RENDER_CLASS: /* Required by recommended tuning setting (not a workaround) */ whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3); - + whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); break; default: break;
As part of the recommended tuning setting, whitelist COMMON_SLICE_CHICKEN1 for MTL/ARL and DG2. The UMD will selectively enable or disable specific bits of the register based on the type of workload and its requirements. v2: Remove the KMD par of enabling specific bits(Matt R) Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)