| Message ID | 82ac9e266f6aca42699ec4a3c8f10887789ee6bf.1724709007.git.jan.kiszka@siemens.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | soc: ti: Add and use PVU on K3-AM65 for DMA isolation | expand |
On Mon, Aug 26, 2024 at 11:50:04PM +0200, Jan Kiszka wrote: > From: Jan Kiszka <jan.kiszka@siemens.com> > > Describe also the VMAP registers which are needed in order to make use > of the PVU with this PCI host. Furthermore, permit to specify a > restricted DMA pool by phandle. That's an ABI break without explanation why it is necessary. > > Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> > --- > .../devicetree/bindings/pci/ti,am65-pci-host.yaml | 13 ++++++++++--- > 1 file changed, 10 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml > index 0a9d10532cc8..72f78f21e1e8 100644 > --- a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml > +++ b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml > @@ -20,7 +20,7 @@ properties: > - ti,keystone-pcie > > reg: > - maxItems: 4 > + maxItems: 6 > > reg-names: > items: > @@ -28,6 +28,8 @@ properties: > - const: dbics > - const: config > - const: atu > + - const: vmap_lp > + - const: vmap_hp > > interrupts: > maxItems: 1 > @@ -69,6 +71,9 @@ properties: > items: > pattern: '^pcie-phy[0-1]$' > > + memory-region: > + description: phandle to restricted DMA pool to be used for all devices behind this controller missing constraints, maxItems Best regards, Krzysztof
On 27.08.24 08:37, Krzysztof Kozlowski wrote: > On Mon, Aug 26, 2024 at 11:50:04PM +0200, Jan Kiszka wrote: >> From: Jan Kiszka <jan.kiszka@siemens.com> >> >> Describe also the VMAP registers which are needed in order to make use >> of the PVU with this PCI host. Furthermore, permit to specify a >> restricted DMA pool by phandle. > > That's an ABI break without explanation why it is necessary. > It is needed in order to support the PVU, as written above. Previous versions of this binding likely didn't consider this use case and therefore didn't describe all registers associated with the hardware. BTW, if you see a way to add the required registers without breaking more than needed, I'm all ears. At least the kernel driver will continue to work with older DTs when you disable PVU support or do not add a DMA pool to the DT. Jan >> >> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> >> --- >> .../devicetree/bindings/pci/ti,am65-pci-host.yaml | 13 ++++++++++--- >> 1 file changed, 10 insertions(+), 3 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml >> index 0a9d10532cc8..72f78f21e1e8 100644 >> --- a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml >> +++ b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml >> @@ -20,7 +20,7 @@ properties: >> - ti,keystone-pcie >> >> reg: >> - maxItems: 4 >> + maxItems: 6 >> >> reg-names: >> items: >> @@ -28,6 +28,8 @@ properties: >> - const: dbics >> - const: config >> - const: atu >> + - const: vmap_lp >> + - const: vmap_hp >> >> interrupts: >> maxItems: 1 >> @@ -69,6 +71,9 @@ properties: >> items: >> pattern: '^pcie-phy[0-1]$' >> >> + memory-region: >> + description: phandle to restricted DMA pool to be used for all devices behind this controller > > missing constraints, maxItems > > Best regards, > Krzysztof >
On 27/08/2024 11:22, Jan Kiszka wrote: > On 27.08.24 08:37, Krzysztof Kozlowski wrote: >> On Mon, Aug 26, 2024 at 11:50:04PM +0200, Jan Kiszka wrote: >>> From: Jan Kiszka <jan.kiszka@siemens.com> >>> >>> Describe also the VMAP registers which are needed in order to make use >>> of the PVU with this PCI host. Furthermore, permit to specify a >>> restricted DMA pool by phandle. >> >> That's an ABI break without explanation why it is necessary. >> > > It is needed in order to support the PVU, as written above. Above say only that you want a new feature and that's not really suitable explanation for ABI break, because answer to this is: add new feature without breaking existing users. But maybe there is a bug or something does not work or never work or there are no users, don't know. > > Previous versions of this binding likely didn't consider this use case > and therefore didn't describe all registers associated with the hardware. > > BTW, if you see a way to add the required registers without breaking > more than needed, I'm all ears. At least the kernel driver will continue > to work with older DTs when you disable PVU support or do not add a DMA > pool to the DT. If there is no ABI break, because driver still handles correctly old DTB, then mention it in the commit msg. Best regards, Krzysztof
On 27.08.24 11:29, Krzysztof Kozlowski wrote: > On 27/08/2024 11:22, Jan Kiszka wrote: >> On 27.08.24 08:37, Krzysztof Kozlowski wrote: >>> On Mon, Aug 26, 2024 at 11:50:04PM +0200, Jan Kiszka wrote: >>>> From: Jan Kiszka <jan.kiszka@siemens.com> >>>> >>>> Describe also the VMAP registers which are needed in order to make use >>>> of the PVU with this PCI host. Furthermore, permit to specify a >>>> restricted DMA pool by phandle. >>> >>> That's an ABI break without explanation why it is necessary. >>> >> >> It is needed in order to support the PVU, as written above. > > Above say only that you want a new feature and that's not really > suitable explanation for ABI break, because answer to this is: add new > feature without breaking existing users. But maybe there is a bug or > something does not work or never work or there are no users, don't know. > >> >> Previous versions of this binding likely didn't consider this use case >> and therefore didn't describe all registers associated with the hardware. >> >> BTW, if you see a way to add the required registers without breaking >> more than needed, I'm all ears. At least the kernel driver will continue >> to work with older DTs when you disable PVU support or do not add a DMA >> pool to the DT. > > If there is no ABI break, because driver still handles correctly old > DTB, then mention it in the commit msg. Well, this is strictly spoken not a topic for this commit because this one should have no clue about what drivers do with DTs according to this binding. But I can put a hint and go into details in the driver patch. Jan
On Tue, Aug 27, 2024 at 11:32:02AM +0200, Jan Kiszka wrote: > On 27.08.24 11:29, Krzysztof Kozlowski wrote: > > On 27/08/2024 11:22, Jan Kiszka wrote: > >> On 27.08.24 08:37, Krzysztof Kozlowski wrote: > >>> On Mon, Aug 26, 2024 at 11:50:04PM +0200, Jan Kiszka wrote: > >>>> From: Jan Kiszka <jan.kiszka@siemens.com> > >>>> > >>>> Describe also the VMAP registers which are needed in order to make use > >>>> of the PVU with this PCI host. Furthermore, permit to specify a > >>>> restricted DMA pool by phandle. > >>> > >>> That's an ABI break without explanation why it is necessary. > >>> > >> > >> It is needed in order to support the PVU, as written above. > > > > Above say only that you want a new feature and that's not really > > suitable explanation for ABI break, because answer to this is: add new > > feature without breaking existing users. But maybe there is a bug or > > something does not work or never work or there are no users, don't know. > > > >> > >> Previous versions of this binding likely didn't consider this use case > >> and therefore didn't describe all registers associated with the hardware. > >> > >> BTW, if you see a way to add the required registers without breaking > >> more than needed, I'm all ears. At least the kernel driver will continue > >> to work with older DTs when you disable PVU support or do not add a DMA > >> pool to the DT. > > > > If there is no ABI break, because driver still handles correctly old > > DTB, then mention it in the commit msg. > > Well, this is strictly spoken not a topic for this commit because this > one should have no clue about what drivers do with DTs according to this > binding. But I can put a hint and go into details in the driver patch. Based on the Techincal Reference Manual for AM654 and the driver implementation in patch 5/6, I think that the following might be one way of hinting that ABI won't break: The PVU on the AM65 SoC is capable of restricting DMA from PCIe devices to specific regions of host memory. Add the optional property "memory-regions" to point to such regions of memory when PVU is used. Since the PVU deals with system physical addresses, utilizing the PVU with PCIe devices also requires setting up the VMAP registers to map the Requester ID of the PCIe device to the CBA Virtual ID, which in turn is mapped to the system physical address. Hence, describe the VMAP registers which are optionally configured whenever PVU is used for PCIe. Regards, Siddharth.
On 27.08.24 08:37, Krzysztof Kozlowski wrote: > On Mon, Aug 26, 2024 at 11:50:04PM +0200, Jan Kiszka wrote: >> From: Jan Kiszka <jan.kiszka@siemens.com> >> >> Describe also the VMAP registers which are needed in order to make use >> of the PVU with this PCI host. Furthermore, permit to specify a >> restricted DMA pool by phandle. > > That's an ABI break without explanation why it is necessary. > >> >> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> >> --- >> .../devicetree/bindings/pci/ti,am65-pci-host.yaml | 13 ++++++++++--- >> 1 file changed, 10 insertions(+), 3 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml >> index 0a9d10532cc8..72f78f21e1e8 100644 >> --- a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml >> +++ b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml >> @@ -20,7 +20,7 @@ properties: >> - ti,keystone-pcie >> >> reg: >> - maxItems: 4 >> + maxItems: 6 >> >> reg-names: >> items: >> @@ -28,6 +28,8 @@ properties: >> - const: dbics >> - const: config >> - const: atu >> + - const: vmap_lp >> + - const: vmap_hp >> >> interrupts: >> maxItems: 1 >> @@ -69,6 +71,9 @@ properties: >> items: >> pattern: '^pcie-phy[0-1]$' >> >> + memory-region: >> + description: phandle to restricted DMA pool to be used for all devices behind this controller > > missing constraints, maxItems > In fact, that was intentional: There could also be multiple region specified here. The driver already handles this. Jan
On 27.08.24 12:06, Siddharth Vadapalli wrote: > On Tue, Aug 27, 2024 at 11:32:02AM +0200, Jan Kiszka wrote: >> On 27.08.24 11:29, Krzysztof Kozlowski wrote: >>> On 27/08/2024 11:22, Jan Kiszka wrote: >>>> On 27.08.24 08:37, Krzysztof Kozlowski wrote: >>>>> On Mon, Aug 26, 2024 at 11:50:04PM +0200, Jan Kiszka wrote: >>>>>> From: Jan Kiszka <jan.kiszka@siemens.com> >>>>>> >>>>>> Describe also the VMAP registers which are needed in order to make use >>>>>> of the PVU with this PCI host. Furthermore, permit to specify a >>>>>> restricted DMA pool by phandle. >>>>> >>>>> That's an ABI break without explanation why it is necessary. >>>>> >>>> >>>> It is needed in order to support the PVU, as written above. >>> >>> Above say only that you want a new feature and that's not really >>> suitable explanation for ABI break, because answer to this is: add new >>> feature without breaking existing users. But maybe there is a bug or >>> something does not work or never work or there are no users, don't know. >>> >>>> >>>> Previous versions of this binding likely didn't consider this use case >>>> and therefore didn't describe all registers associated with the hardware. >>>> >>>> BTW, if you see a way to add the required registers without breaking >>>> more than needed, I'm all ears. At least the kernel driver will continue >>>> to work with older DTs when you disable PVU support or do not add a DMA >>>> pool to the DT. >>> >>> If there is no ABI break, because driver still handles correctly old >>> DTB, then mention it in the commit msg. >> >> Well, this is strictly spoken not a topic for this commit because this >> one should have no clue about what drivers do with DTs according to this >> binding. But I can put a hint and go into details in the driver patch. > > Based on the Techincal Reference Manual for AM654 and the driver > implementation in patch 5/6, I think that the following might be one way > of hinting that ABI won't break: > > The PVU on the AM65 SoC is capable of restricting DMA from PCIe devices to > specific regions of host memory. Add the optional property "memory-regions" > to point to such regions of memory when PVU is used. Since the PVU deals > with system physical addresses, utilizing the PVU with PCIe devices also > requires setting up the VMAP registers to map the Requester ID of the > PCIe device to the CBA Virtual ID, which in turn is mapped to the system > physical address. Hence, describe the VMAP registers which are optionally > configured whenever PVU is used for PCIe. Thanks, will reuse this! Additionally, we should then likely do reg: minItems: 4 maxItems: 6 to underline that the old form is still fine. Do I need to do anything to reg-names then as well? Jan
On 27/08/2024 12:46, Jan Kiszka wrote: > On 27.08.24 12:06, Siddharth Vadapalli wrote: >> On Tue, Aug 27, 2024 at 11:32:02AM +0200, Jan Kiszka wrote: >>> On 27.08.24 11:29, Krzysztof Kozlowski wrote: >>>> On 27/08/2024 11:22, Jan Kiszka wrote: >>>>> On 27.08.24 08:37, Krzysztof Kozlowski wrote: >>>>>> On Mon, Aug 26, 2024 at 11:50:04PM +0200, Jan Kiszka wrote: >>>>>>> From: Jan Kiszka <jan.kiszka@siemens.com> >>>>>>> >>>>>>> Describe also the VMAP registers which are needed in order to make use >>>>>>> of the PVU with this PCI host. Furthermore, permit to specify a >>>>>>> restricted DMA pool by phandle. >>>>>> >>>>>> That's an ABI break without explanation why it is necessary. >>>>>> >>>>> >>>>> It is needed in order to support the PVU, as written above. >>>> >>>> Above say only that you want a new feature and that's not really >>>> suitable explanation for ABI break, because answer to this is: add new >>>> feature without breaking existing users. But maybe there is a bug or >>>> something does not work or never work or there are no users, don't know. >>>> >>>>> >>>>> Previous versions of this binding likely didn't consider this use case >>>>> and therefore didn't describe all registers associated with the hardware. >>>>> >>>>> BTW, if you see a way to add the required registers without breaking >>>>> more than needed, I'm all ears. At least the kernel driver will continue >>>>> to work with older DTs when you disable PVU support or do not add a DMA >>>>> pool to the DT. >>>> >>>> If there is no ABI break, because driver still handles correctly old >>>> DTB, then mention it in the commit msg. >>> >>> Well, this is strictly spoken not a topic for this commit because this >>> one should have no clue about what drivers do with DTs according to this >>> binding. But I can put a hint and go into details in the driver patch. >> >> Based on the Techincal Reference Manual for AM654 and the driver >> implementation in patch 5/6, I think that the following might be one way >> of hinting that ABI won't break: >> >> The PVU on the AM65 SoC is capable of restricting DMA from PCIe devices to >> specific regions of host memory. Add the optional property "memory-regions" >> to point to such regions of memory when PVU is used. Since the PVU deals >> with system physical addresses, utilizing the PVU with PCIe devices also >> requires setting up the VMAP registers to map the Requester ID of the >> PCIe device to the CBA Virtual ID, which in turn is mapped to the system >> physical address. Hence, describe the VMAP registers which are optionally >> configured whenever PVU is used for PCIe. > > Thanks, will reuse this! > > Additionally, we should then likely do > > reg: > minItems: 4 > maxItems: 6 > > to underline that the old form is still fine. Do I need to do anything > to reg-names then as well? They need "minItems: 4". Best regards, Krzysztof
On 27/08/2024 12:44, Jan Kiszka wrote: >>> maxItems: 1 >>> @@ -69,6 +71,9 @@ properties: >>> items: >>> pattern: '^pcie-phy[0-1]$' >>> >>> + memory-region: >>> + description: phandle to restricted DMA pool to be used for all devices behind this controller >> >> missing constraints, maxItems >> > > In fact, that was intentional: There could also be multiple region > specified here. The driver already handles this. Then list the items with description and minItems: 1. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml index 0a9d10532cc8..72f78f21e1e8 100644 --- a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml @@ -20,7 +20,7 @@ properties: - ti,keystone-pcie reg: - maxItems: 4 + maxItems: 6 reg-names: items: @@ -28,6 +28,8 @@ properties: - const: dbics - const: config - const: atu + - const: vmap_lp + - const: vmap_hp interrupts: maxItems: 1 @@ -69,6 +71,9 @@ properties: items: pattern: '^pcie-phy[0-1]$' + memory-region: + description: phandle to restricted DMA pool to be used for all devices behind this controller + required: - compatible - reg @@ -104,8 +109,10 @@ examples: reg = <0x5500000 0x1000>, <0x5501000 0x1000>, <0x10000000 0x2000>, - <0x5506000 0x1000>; - reg-names = "app", "dbics", "config", "atu"; + <0x5506000 0x1000>, + <0x2900000 0x1000>, + <0x2908000 0x1000>; + reg-names = "app", "dbics", "config", "atu", "vmap_lp", "vmap_hp"; power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; #address-cells = <3>; #size-cells = <2>;