| Message ID | 20240801203008.11224-14-kowal@linux.ibm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | XIVE2 changes for TIMA operations | expand |
On 8/1/24 22:30, Michael Kowal wrote: > Some of the TIMA Special CI operations perform the same operation at > alternative byte offsets and lengths. The following > xive2_tm_opertions[] table entries are missing when they exist for > other offsets/sizes and have been added: > - lwz@0x810 Pull/Invalidate O/S Context to register added > lwz@0x818 exists > ld @0x818 exists > - lwz@0x820 Pull Pool Context to register added > lwz@0x828 exists > ld @0x828 exists > - lwz@0x830 Pull Thread Context to register added > lbz@0x838 exists > > Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Thanks, C. > --- > include/hw/ppc/xive_regs.h | 7 ++++++- > hw/intc/xive.c | 6 ++++++ > 2 files changed, 12 insertions(+), 1 deletion(-) > > diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h > index 5b11463777..326327fc79 100644 > --- a/include/hw/ppc/xive_regs.h > +++ b/include/hw/ppc/xive_regs.h > @@ -124,12 +124,17 @@ > #define TM_SPC_PULL_USR_CTX 0x808 /* Load32 Pull/Invalidate user */ > /* context */ > #define TM_SPC_SET_OS_PENDING 0x812 /* Store8 Set OS irq pending bit */ > +#define TM_SPC_PULL_OS_CTX_G2 0x810 /* Load32/Load64 Pull/Invalidate OS */ > + /* context to reg */ > #define TM_SPC_PULL_OS_CTX 0x818 /* Load32/Load64 Pull/Invalidate OS */ > /* context to reg */ > +#define TM_SPC_PULL_POOL_CTX_G2 0x820 /* Load32/Load64 Pull/Invalidate Pool */ > + /* context to reg */ > #define TM_SPC_PULL_POOL_CTX 0x828 /* Load32/Load64 Pull/Invalidate Pool */ > /* context to reg */ > #define TM_SPC_ACK_HV_REG 0x830 /* Load16 ack HV irq to reg */ > -#define TM_SPC_PULL_PHYS_CTX 0x838 /* Pull phys ctx to reg */ > +#define TM_SPC_PULL_PHYS_CTX_G2 0x830 /* Load32 Pull phys ctx to reg */ > +#define TM_SPC_PULL_PHYS_CTX 0x838 /* Load8 Pull phys ctx to reg */ > #define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd */ > /* line */ > #define TM_SPC_ACK_OS_EL 0xc10 /* Store8 ack OS irq to even line */ > diff --git a/hw/intc/xive.c b/hw/intc/xive.c > index 99c8bea598..ce1504fbed 100644 > --- a/hw/intc/xive.c > +++ b/hw/intc/xive.c > @@ -614,18 +614,24 @@ static const XiveTmOp xive2_tm_operations[] = { > xive_tm_ack_os_reg }, > { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, > NULL }, > + { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX_G2, 4, NULL, > + xive2_tm_pull_os_ctx }, > { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, > xive2_tm_pull_os_ctx }, > { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, > xive2_tm_pull_os_ctx }, > { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, > xive_tm_ack_hv_reg }, > + { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX_G2, 4, NULL, > + xive_tm_pull_pool_ctx }, > { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, > xive_tm_pull_pool_ctx }, > { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, > xive_tm_pull_pool_ctx }, > { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX_OL, 1, xive2_tm_pull_os_ctx_ol, > NULL }, > + { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX_G2, 4, NULL, > + xive_tm_pull_phys_ctx }, > { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX, 1, NULL, > xive_tm_pull_phys_ctx }, > { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX_OL, 1, xive2_tm_pull_phys_ctx_ol,
diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index 5b11463777..326327fc79 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -124,12 +124,17 @@ #define TM_SPC_PULL_USR_CTX 0x808 /* Load32 Pull/Invalidate user */ /* context */ #define TM_SPC_SET_OS_PENDING 0x812 /* Store8 Set OS irq pending bit */ +#define TM_SPC_PULL_OS_CTX_G2 0x810 /* Load32/Load64 Pull/Invalidate OS */ + /* context to reg */ #define TM_SPC_PULL_OS_CTX 0x818 /* Load32/Load64 Pull/Invalidate OS */ /* context to reg */ +#define TM_SPC_PULL_POOL_CTX_G2 0x820 /* Load32/Load64 Pull/Invalidate Pool */ + /* context to reg */ #define TM_SPC_PULL_POOL_CTX 0x828 /* Load32/Load64 Pull/Invalidate Pool */ /* context to reg */ #define TM_SPC_ACK_HV_REG 0x830 /* Load16 ack HV irq to reg */ -#define TM_SPC_PULL_PHYS_CTX 0x838 /* Pull phys ctx to reg */ +#define TM_SPC_PULL_PHYS_CTX_G2 0x830 /* Load32 Pull phys ctx to reg */ +#define TM_SPC_PULL_PHYS_CTX 0x838 /* Load8 Pull phys ctx to reg */ #define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd */ /* line */ #define TM_SPC_ACK_OS_EL 0xc10 /* Store8 ack OS irq to even line */ diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 99c8bea598..ce1504fbed 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -614,18 +614,24 @@ static const XiveTmOp xive2_tm_operations[] = { xive_tm_ack_os_reg }, { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, NULL }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX_G2, 4, NULL, + xive2_tm_pull_os_ctx }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, xive2_tm_pull_os_ctx }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, xive2_tm_pull_os_ctx }, { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, xive_tm_ack_hv_reg }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX_G2, 4, NULL, + xive_tm_pull_pool_ctx }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, xive_tm_pull_pool_ctx }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_ctx }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX_OL, 1, xive2_tm_pull_os_ctx_ol, NULL }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX_G2, 4, NULL, + xive_tm_pull_phys_ctx }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX, 1, NULL, xive_tm_pull_phys_ctx }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX_OL, 1, xive2_tm_pull_phys_ctx_ol,
Some of the TIMA Special CI operations perform the same operation at alternative byte offsets and lengths. The following xive2_tm_opertions[] table entries are missing when they exist for other offsets/sizes and have been added: - lwz@0x810 Pull/Invalidate O/S Context to register added lwz@0x818 exists ld @0x818 exists - lwz@0x820 Pull Pool Context to register added lwz@0x828 exists ld @0x828 exists - lwz@0x830 Pull Thread Context to register added lbz@0x838 exists Signed-off-by: Michael Kowal <kowal@linux.ibm.com> --- include/hw/ppc/xive_regs.h | 7 ++++++- hw/intc/xive.c | 6 ++++++ 2 files changed, 12 insertions(+), 1 deletion(-)