| Message ID | 20240828203721.2751904-1-quic_nkela@quicinc.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | arm64: qcom: Introduce SA8255p Ride platform | expand |
On 28/08/2024 22:36, Nikunj Kela wrote: > This series enables the support for SA8255p Qualcomm SoC and Ride > platform. This platform uses SCMI power, reset, performance, sensor > protocols for resources(e.g. clocks, regulator, interconnect, phy etc.) > management. SA8255p is a virtual platforms that uses Qualcomm smc/hvc > transport driver. > Who is supposed to merge it? The Cc-list is quite enormous and I got now 20 bounces: " Too many recipients to the message" at least drop some non-maintainer related, I counted 5-7 Qualcomm ones which should not be needed. Best regards, Krzysztof
On 8/29/2024 12:57 AM, Krzysztof Kozlowski wrote: > On 28/08/2024 22:36, Nikunj Kela wrote: >> This series enables the support for SA8255p Qualcomm SoC and Ride >> platform. This platform uses SCMI power, reset, performance, sensor >> protocols for resources(e.g. clocks, regulator, interconnect, phy etc.) >> management. SA8255p is a virtual platforms that uses Qualcomm smc/hvc >> transport driver. >> > Who is supposed to merge it? The Cc-list is quite enormous and I got now > 20 bounces: > > " Too many recipients to the message" > > at least drop some non-maintainer related, I counted 5-7 Qualcomm ones > which should not be needed. > > Best regards, > Krzysztof Hi Krzysztof, I ran maintainers script to get all the emails. I kept maintainers, reviewers and "in file" ones in addition to some Qualcomm leads. I will drop "in file" and Qualcomm leads in next version. Thanks, -Nikunj
This series enables the support for SA8255p Qualcomm SoC and Ride platform. This platform uses SCMI power, reset, performance, sensor protocols for resources(e.g. clocks, regulator, interconnect, phy etc.) management. SA8255p is a virtual platforms that uses Qualcomm smc/hvc transport driver. Multiple virtual SCMI instances are being used to achieve the parallelism. SCMI platform stack runs in SMP enabled VM hence allows platform to service multiple resource requests in parallel. Each device is assigned its own dedicated SCMI channel and Tx/Rx doorbells. Resource operations are grouped together to achieve better abstraction and to reduce the number of requests being sent to SCMI platform(server) thus improving boot time KPIs. This design approach was presented during LinaroConnect 2024 conference[1]. Architecture: ------------ +--------------------+ | Shared Memory | | | | +----------------+ | +----------------------------------+ +----------------------------+ +-+-> ufs-shmem <-+---+ | Linux VM | | Firmware VM | | | +----------------+ | | | +----------+ +----------+ | | | | | | | | | UFS | | PCIe | | | +---------+ f +----------+ | | | | | | | Driver | | Driver | | | |Drivers <---+ SCMI | | e | | | | | | +--+----^--+ +----------+ | | | (clks, | g | Server +-+---------------------+ | | | | | | | | | vreg, +---> | | h | | | b|k | a| l| | | | gpio, | +--^-----+-+ | | | | | | | | | | phy, | | | | | | | | | +---v----+----+ +----------+ | | | etc.) | | | | | | +------------+--+ UFS SCMI | | PCIe SCMI| | | +---------+ | | | | | | | INSTANCE | | INSTANCE | | | | | | | +---------------+ | | +-^-----+-----+ +----------+ | | | | | | | pcie-shmem | | | | | | +------------------+-----+---+ | +---------------+ | +----+-----+-----------------------+ | | | | | | | | +--------------------+ | | d|IRQ i|HVC j|IRQ c|HVC | | | | | | | | +-----------------------+-----v----------------------------------------------------------------------+-----v------------------------------+ | | | | | | | HYPERVISOR | | | | | +-----------------------------------------------------------------------------------------------------------------------------------------+ +--------+ +--------+ +----------+ +-----------+ | CLOCK | | PHY | | UFS | | PCIe | +--------+ +--------+ +----------+ +-----------+ This series is based on next-20240828. [1]: https://resources.linaro.org/en/resource/wfnfEwBhRjLV1PEAJoDDte Nikunj Kela (22): dt-bindings: arm: qcom: add the SoC ID for SA8255P soc: qcom: socinfo: add support for SA8255P dt-bindings: arm: qcom: add SA8255p Ride board dt-bindings: firmware: qcom,scm: document support for SA8255p dt-bindings: mailbox: qcom-ipcc: document the support for SA8255p dt-bindings: watchdog: qcom-wdt: document support on SA8255p dt-bindings: crypto: qcom,prng: document support for SA8255p dt-bindings: interrupt-controller: qcom-pdc: document support for SA8255p dt-bindings: soc: qcom: aoss-qmp: document support for SA8255p dt-bindings: pinctrl: document support for SA8255p pinctrl: qcom: sa8775p: Add support for SA8255p SoC dt-bindings: cpufreq: qcom-hw: document support for SA8255p dt-bindings: thermal: tsens: document support on SA8255p dt-bindings: arm-smmu: document the support on SA8255p dt-bindings: mfd: qcom,tcsr: document support for SA8255p dt-bindings: qcom: geni-se: document support for SA8255P dt-bindings: serial: document support for SA8255p dt-bindings: spi: document support for SA8255p dt-bindings: i2c: document support for SA8255p dt-bindings: firmware: arm,scmi: allow multiple virtual instances ARM: dt: GIC: add extended SPI specifier arm64: dts: qcom: Add reduced functional DT for SA8255p Ride platform .../devicetree/bindings/arm/qcom.yaml | 6 + .../bindings/cpufreq/cpufreq-qcom-hw.yaml | 1 + .../devicetree/bindings/crypto/qcom,prng.yaml | 1 + .../bindings/firmware/arm,scmi.yaml | 2 +- .../bindings/firmware/qcom,scm.yaml | 2 + .../bindings/i2c/qcom,i2c-geni-qcom.yaml | 56 +- .../interrupt-controller/qcom,pdc.yaml | 1 + .../devicetree/bindings/iommu/arm,smmu.yaml | 3 + .../bindings/mailbox/qcom-ipcc.yaml | 1 + .../devicetree/bindings/mfd/qcom,tcsr.yaml | 1 + .../bindings/pinctrl/qcom,sa8775p-tlmm.yaml | 4 +- .../serial/qcom,serial-geni-qcom.yaml | 58 +- .../bindings/soc/qcom/qcom,aoss-qmp.yaml | 1 + .../bindings/soc/qcom/qcom,geni-se.yaml | 47 +- .../bindings/spi/qcom,spi-geni-qcom.yaml | 64 +- .../bindings/thermal/qcom-tsens.yaml | 1 + .../bindings/watchdog/qcom-wdt.yaml | 1 + arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi | 80 + arch/arm64/boot/dts/qcom/sa8255p-ride.dts | 149 + arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi | 2312 ++++++++++++++++ arch/arm64/boot/dts/qcom/sa8255p.dtsi | 2405 +++++++++++++++++ drivers/pinctrl/qcom/pinctrl-sa8775p.c | 1 + drivers/soc/qcom/socinfo.c | 1 + include/dt-bindings/arm/qcom,ids.h | 1 + .../interrupt-controller/arm-gic.h | 1 + 26 files changed, 5157 insertions(+), 44 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-ride.dts create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi create mode 100644 arch/arm64/boot/dts/qcom/sa8255p.dtsi base-commit: 195a402a75791e6e0d96d9da27ca77671bc656a8