| Message ID | 20240813164244.751597-3-coltonlewis@google.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Extend pmu_counters_test to AMD CPUs | expand |
On Tue, Aug 13, 2024, Colton Lewis wrote: > This defined the CPUID calls to determine what extensions and > properties are available. AMD reference manual names listed below. > > * PerfCtrExtCore (six core counters instead of four) > * PerfCtrExtNB (four counters for northbridge events) > * PerfCtrExtL2I (four counters for L2 cache events) > * PerfMonV2 (support for registers to control multiple > counters with a single register write) > * LbrAndPmcFreeze (support for freezing last branch recorded stack on > performance counter overflow) > * NumPerfCtrCore (number of core counters) > * NumPerfCtrNB (number of northbridge counters) > > Signed-off-by: Colton Lewis <coltonlewis@google.com> > --- > tools/testing/selftests/kvm/include/x86_64/processor.h | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/tools/testing/selftests/kvm/include/x86_64/processor.h b/tools/testing/selftests/kvm/include/x86_64/processor.h > index a0c1440017bb..9d87b5f8974f 100644 > --- a/tools/testing/selftests/kvm/include/x86_64/processor.h > +++ b/tools/testing/selftests/kvm/include/x86_64/processor.h > @@ -183,6 +183,9 @@ struct kvm_x86_cpu_feature { > #define X86_FEATURE_GBPAGES KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 26) > #define X86_FEATURE_RDTSCP KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 27) > #define X86_FEATURE_LM KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 29) > +#define X86_FEATURE_PERF_CTR_EXT_CORE KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 23) > +#define X86_FEATURE_PERF_CTR_EXT_NB KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 24) > +#define X86_FEATURE_PERF_CTR_EXT_L2I KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 28) You won't be testing Northbridge counters and L2I counters, so these two could be optional to the patch. > #define X86_FEATURE_INVTSC KVM_X86_CPU_FEATURE(0x80000007, 0, EDX, 8) > #define X86_FEATURE_RDPRU KVM_X86_CPU_FEATURE(0x80000008, 0, EBX, 4) > #define X86_FEATURE_AMD_IBPB KVM_X86_CPU_FEATURE(0x80000008, 0, EBX, 12) > @@ -195,6 +198,8 @@ struct kvm_x86_cpu_feature { > #define X86_FEATURE_VGIF KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 16) > #define X86_FEATURE_SEV KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 1) > #define X86_FEATURE_SEV_ES KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 3) > +#define X86_FEATURE_PERF_MON_V2 KVM_X86_CPU_FEATURE(0x80000022, 0, EAX, 0) Let's use X86_FEATURE_PERFMON_V2 instead. > +#define X86_FEATURE_PERF_LBR_PMC_FREEZE KVM_X86_CPU_FEATURE(0x80000022, 0, EAX, 2) You don't use this feature, do you? If not, this can be optional for the patch. > > /* > * KVM defined paravirt features. > @@ -281,6 +286,8 @@ struct kvm_x86_cpu_property { > #define X86_PROPERTY_GUEST_MAX_PHY_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 16, 23) > #define X86_PROPERTY_SEV_C_BIT KVM_X86_CPU_PROPERTY(0x8000001F, 0, EBX, 0, 5) > #define X86_PROPERTY_PHYS_ADDR_REDUCTION KVM_X86_CPU_PROPERTY(0x8000001F, 0, EBX, 6, 11) > +#define X86_PROPERTY_NUM_PERF_CTR_CORE KVM_X86_CPU_PROPERTY(0x80000022, 0, EBX, 0, 3) > +#define X86_PROPERTY_NUM_PERF_CTR_NB KVM_X86_CPU_PROPERTY(0x80000022, 0, EBX, 10, 15) > ditto. > #define X86_PROPERTY_MAX_CENTAUR_LEAF KVM_X86_CPU_PROPERTY(0xC0000000, 0, EAX, 0, 31) > > -- > 2.46.0.76.ge559c4bf1a-goog >
On Wed, Aug 28, 2024, Colton Lewis wrote: > Hi Mingwei, thanks for reviewing! > > Mingwei Zhang <mizhang@google.com> writes: > > > On Tue, Aug 13, 2024, Colton Lewis wrote: > > > This defined the CPUID calls to determine what extensions and > > > properties are available. AMD reference manual names listed below. > > > > * PerfCtrExtCore (six core counters instead of four) > > > * PerfCtrExtNB (four counters for northbridge events) > > > * PerfCtrExtL2I (four counters for L2 cache events) > > > * PerfMonV2 (support for registers to control multiple > > > counters with a single register write) > > > * LbrAndPmcFreeze (support for freezing last branch recorded stack on > > > performance counter overflow) > > > * NumPerfCtrCore (number of core counters) > > > * NumPerfCtrNB (number of northbridge counters) > > > > Signed-off-by: Colton Lewis <coltonlewis@google.com> > > > --- > > > tools/testing/selftests/kvm/include/x86_64/processor.h | 7 +++++++ > > > 1 file changed, 7 insertions(+) > > > > diff --git a/tools/testing/selftests/kvm/include/x86_64/processor.h > > > b/tools/testing/selftests/kvm/include/x86_64/processor.h > > > index a0c1440017bb..9d87b5f8974f 100644 > > > --- a/tools/testing/selftests/kvm/include/x86_64/processor.h > > > +++ b/tools/testing/selftests/kvm/include/x86_64/processor.h > > > @@ -183,6 +183,9 @@ struct kvm_x86_cpu_feature { > > > #define X86_FEATURE_GBPAGES KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 26) > > > #define X86_FEATURE_RDTSCP KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 27) > > > #define X86_FEATURE_LM KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 29) > > > +#define X86_FEATURE_PERF_CTR_EXT_CORE KVM_X86_CPU_FEATURE(0x80000001, > > > 0, ECX, 23) > > > +#define X86_FEATURE_PERF_CTR_EXT_NB KVM_X86_CPU_FEATURE(0x80000001, > > > 0, ECX, 24) > > > +#define X86_FEATURE_PERF_CTR_EXT_L2I KVM_X86_CPU_FEATURE(0x80000001, > > > 0, ECX, 28) > > > You won't be testing Northbridge counters and L2I counters, so these two > > could be optional to the patch. > > That's correct. Since it was a small thing to include I thought it best > to include and save someone in the future from digging through the > reference manual again. +1. They're defines, i.e. have no meaningful cost. And anything that *might* save me from having to find CPUID entries in the SDM/APM is worth adding.
diff --git a/tools/testing/selftests/kvm/include/x86_64/processor.h b/tools/testing/selftests/kvm/include/x86_64/processor.h index a0c1440017bb..9d87b5f8974f 100644 --- a/tools/testing/selftests/kvm/include/x86_64/processor.h +++ b/tools/testing/selftests/kvm/include/x86_64/processor.h @@ -183,6 +183,9 @@ struct kvm_x86_cpu_feature { #define X86_FEATURE_GBPAGES KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 26) #define X86_FEATURE_RDTSCP KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 27) #define X86_FEATURE_LM KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 29) +#define X86_FEATURE_PERF_CTR_EXT_CORE KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 23) +#define X86_FEATURE_PERF_CTR_EXT_NB KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 24) +#define X86_FEATURE_PERF_CTR_EXT_L2I KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 28) #define X86_FEATURE_INVTSC KVM_X86_CPU_FEATURE(0x80000007, 0, EDX, 8) #define X86_FEATURE_RDPRU KVM_X86_CPU_FEATURE(0x80000008, 0, EBX, 4) #define X86_FEATURE_AMD_IBPB KVM_X86_CPU_FEATURE(0x80000008, 0, EBX, 12) @@ -195,6 +198,8 @@ struct kvm_x86_cpu_feature { #define X86_FEATURE_VGIF KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 16) #define X86_FEATURE_SEV KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 1) #define X86_FEATURE_SEV_ES KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 3) +#define X86_FEATURE_PERF_MON_V2 KVM_X86_CPU_FEATURE(0x80000022, 0, EAX, 0) +#define X86_FEATURE_PERF_LBR_PMC_FREEZE KVM_X86_CPU_FEATURE(0x80000022, 0, EAX, 2) /* * KVM defined paravirt features. @@ -281,6 +286,8 @@ struct kvm_x86_cpu_property { #define X86_PROPERTY_GUEST_MAX_PHY_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 16, 23) #define X86_PROPERTY_SEV_C_BIT KVM_X86_CPU_PROPERTY(0x8000001F, 0, EBX, 0, 5) #define X86_PROPERTY_PHYS_ADDR_REDUCTION KVM_X86_CPU_PROPERTY(0x8000001F, 0, EBX, 6, 11) +#define X86_PROPERTY_NUM_PERF_CTR_CORE KVM_X86_CPU_PROPERTY(0x80000022, 0, EBX, 0, 3) +#define X86_PROPERTY_NUM_PERF_CTR_NB KVM_X86_CPU_PROPERTY(0x80000022, 0, EBX, 10, 15) #define X86_PROPERTY_MAX_CENTAUR_LEAF KVM_X86_CPU_PROPERTY(0xC0000000, 0, EAX, 0, 31)
This defined the CPUID calls to determine what extensions and properties are available. AMD reference manual names listed below. * PerfCtrExtCore (six core counters instead of four) * PerfCtrExtNB (four counters for northbridge events) * PerfCtrExtL2I (four counters for L2 cache events) * PerfMonV2 (support for registers to control multiple counters with a single register write) * LbrAndPmcFreeze (support for freezing last branch recorded stack on performance counter overflow) * NumPerfCtrCore (number of core counters) * NumPerfCtrNB (number of northbridge counters) Signed-off-by: Colton Lewis <coltonlewis@google.com> --- tools/testing/selftests/kvm/include/x86_64/processor.h | 7 +++++++ 1 file changed, 7 insertions(+)