| Message ID | 20240830130218.3377060-6-claudiu.beznea.uj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | Add RTC support for the Renesas RZ/G3S SoC | expand |
On Fri, 30 Aug 2024 16:02:11 +0300, Claudiu wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > Document the RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC. > The RTC IP available on Renesas RZ/V2H is almost identical with the > one found on Renesas RZ/G3S (it misses the time capture functionality > which is not yet implemented on proposed driver). For this, added also a > generic compatible that will be used at the moment as fallback for both > RZ/G3S and RZ/V2H. > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > --- > > Changes in v3: > - added RTC bus clock, reset and power-domain; it has been detected > by reverse engineering that RTC and VBATTB clock, reset and power > domain are shared; HW manual doesn't mention it > - updated example with these and with assigned-clock properties > needed to configure the VBATTCLK MUX with proper parent > - updated example section with dt-bindings/clock/r9a08g045-cpg.h > and dt-bindings/clock/r9a08g045-vbattb.h includes > - for all these, dropped Conor's Rb tag > > Changes in v2: > - updated patch description and title > - included reference to rtc.yaml > - updated compatible list with a generic compatible as explained in > patch description; with this the node in examples section has also been > updated > - used items to describe interrupts, interrupt-names, clock, clock-names > - updated title section > > .../bindings/rtc/renesas,rz-rtca3.yaml | 86 +++++++++++++++++++ > 1 file changed, 86 insertions(+) > create mode 100644 Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml > Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Hi Claudiu, On Fri, Aug 30, 2024 at 3:02 PM Claudiu <claudiu.beznea@tuxon.dev> wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > Document the RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC. > The RTC IP available on Renesas RZ/V2H is almost identical with the > one found on Renesas RZ/G3S (it misses the time capture functionality > which is not yet implemented on proposed driver). For this, added also a > generic compatible that will be used at the moment as fallback for both > RZ/G3S and RZ/V2H. > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > --- > > Changes in v3: > - added RTC bus clock, reset and power-domain; it has been detected > by reverse engineering that RTC and VBATTB clock, reset and power > domain are shared; HW manual doesn't mention it > - updated example with these and with assigned-clock properties > needed to configure the VBATTCLK MUX with proper parent > - updated example section with dt-bindings/clock/r9a08g045-cpg.h > and dt-bindings/clock/r9a08g045-vbattb.h includes > - for all these, dropped Conor's Rb tag Thanks for the update! Sorry for chiming in late, but this RTCA-3 block seems to be a derivative of the RTC blocks found on older SuperH SoCs, and on RZ/A1 and RZ/A2 ARM SoCs. Differences are found in (lack of) 100/1000-year-count parts and the Year Alarm Enable Register, and in some control register bits. The SuperH and RZ/A1 variant is supported by drivers/rtc/rtc-sh.c; DT bindings for the latter are found in Documentation/devicetree/bindings/rtc/renesas,sh-rtc.yaml. (My first guess was that RTC-A1 is used on RZ/A1, RTC-A2 on RZ/A2, and RTC-A3 on RZ/A3, but apparently RZ/A3UL does not have an RTC... Oh well, at least it is used on later RZ series SoCs...) Gr{oetje,eeting}s, Geert
Hi, Geert, On 10.10.2024 12:29, Geert Uytterhoeven wrote: > Hi Claudiu, > > On Fri, Aug 30, 2024 at 3:02 PM Claudiu <claudiu.beznea@tuxon.dev> wrote: >> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> >> >> Document the RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC. >> The RTC IP available on Renesas RZ/V2H is almost identical with the >> one found on Renesas RZ/G3S (it misses the time capture functionality >> which is not yet implemented on proposed driver). For this, added also a >> generic compatible that will be used at the moment as fallback for both >> RZ/G3S and RZ/V2H. >> >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> >> --- >> >> Changes in v3: >> - added RTC bus clock, reset and power-domain; it has been detected >> by reverse engineering that RTC and VBATTB clock, reset and power >> domain are shared; HW manual doesn't mention it >> - updated example with these and with assigned-clock properties >> needed to configure the VBATTCLK MUX with proper parent >> - updated example section with dt-bindings/clock/r9a08g045-cpg.h >> and dt-bindings/clock/r9a08g045-vbattb.h includes >> - for all these, dropped Conor's Rb tag > > Thanks for the update! > > Sorry for chiming in late, but this RTCA-3 block seems to be a > derivative of the RTC blocks found on older SuperH SoCs, and on RZ/A1 > and RZ/A2 ARM SoCs. Differences are found in (lack of) > 100/1000-year-count parts and the Year Alarm Enable Register, and in > some control register bits. At a 1st look it seems so, yes. I was inclined at the beginning to just use the rtc-sh but the RZ/G3S HW manual mentions a lot of restrictions that need to be followed when configuring the IP. Because of these restrictions I chose to have a different driver. Otherwise the rtc-sh would have become way too complication as far as I can tell. From these restriction I can mention: - wait for 2*1/64 periods when configuring the alarm - from HW manual: When the RCR1 register is modified, check that all the bits have been updated before proceeding to the next processing - from HW manual: section 22.6.4. Notes on writing to and reading from registers) after writing to count registers, alarm registers, year alarm enable register, bits RCR2.AADJE, AADJP, and HR24 register, we need to do 3 empty reads before being able to fetch the registers content. - updates to RCR2.START need to be checked before continuing (note 2 from HW manual on RCR2 register: After writing to this bit, confirm that its value has actually changed before proceeding with further processing) - there are many bits that are synchronized w/ count source and need to be checked before proceeding (when setting it up). - According to HW manual (section 22.4.2. Clock and count mode setting procedure) we need to wait at least 6 cycles of the 32KHz clock after clock was enabled. - According to HW manual (section 22.3.19. RTC Control Register 2) when set 24 hours mode this needs to be done separate from stop operation. - According to HW manual (section 22.6.3. Notes on writing to and reading from registers) after reset we need to wait 6 clock cycles before writing to RTC registers. - According to HW manual (section 22.6.4. Notes on writing to and reading from registers) we need to wait 1/128 seconds while the clock is operating (RCR2.START bit = 1) to be able to read the counters after a return from reset. - and there are other restrictions Thank you, Claudiu Beznea > > The SuperH and RZ/A1 variant is supported by drivers/rtc/rtc-sh.c; > DT bindings for the latter are found in > Documentation/devicetree/bindings/rtc/renesas,sh-rtc.yaml. > > (My first guess was that RTC-A1 is used on RZ/A1, RTC-A2 on RZ/A2, > and RTC-A3 on RZ/A3, but apparently RZ/A3UL does not have an RTC... > Oh well, at least it is used on later RZ series SoCs...) > > Gr{oetje,eeting}s, > > Geert >
Hi Claudiu, On Thu, Oct 10, 2024 at 11:52 AM claudiu beznea <claudiu.beznea@tuxon.dev> wrote: > On 10.10.2024 12:29, Geert Uytterhoeven wrote: > > On Fri, Aug 30, 2024 at 3:02 PM Claudiu <claudiu.beznea@tuxon.dev> wrote: > >> Document the RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC. > >> The RTC IP available on Renesas RZ/V2H is almost identical with the > >> one found on Renesas RZ/G3S (it misses the time capture functionality > >> which is not yet implemented on proposed driver). For this, added also a > >> generic compatible that will be used at the moment as fallback for both > >> RZ/G3S and RZ/V2H. > > Sorry for chiming in late, but this RTCA-3 block seems to be a > > derivative of the RTC blocks found on older SuperH SoCs, and on RZ/A1 > > and RZ/A2 ARM SoCs. Differences are found in (lack of) > > 100/1000-year-count parts and the Year Alarm Enable Register, and in > > some control register bits. > > At a 1st look it seems so, yes. I was inclined at the beginning to just use > the rtc-sh but the RZ/G3S HW manual mentions a lot of restrictions that > need to be followed when configuring the IP. Because of these restrictions > I chose to have a different driver. Otherwise the rtc-sh would have become > way too complication as far as I can tell. [...] Thank you, makes sense! Gr{oetje,eeting}s, Geert
diff --git a/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml b/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml new file mode 100644 index 000000000000..bc99795dfb6b --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/renesas,rz-rtca3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RTCA-3 Real Time Clock + +maintainers: + - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> + +allOf: + - $ref: rtc.yaml# + +properties: + compatible: + items: + - enum: + - renesas,r9a08g045-rtca3 # RZ/G3S + - const: renesas,rz-rtca3 + + reg: + maxItems: 1 + + interrupts: + items: + - description: Alarm interrupt + - description: Periodic interrupt + - description: Carry interrupt + + interrupt-names: + items: + - const: alarm + - const: period + - const: carry + + clocks: + items: + - description: RTC bus clock + - description: RTC counter clock + + clock-names: + items: + - const: bus + - const: counter + + power-domains: + maxItems: 1 + + resets: + items: + - description: VBATTB module reset + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r9a08g045-cpg.h> + #include <dt-bindings/clock/r9a08g045-vbattb.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + rtc@1004ec00 { + compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3"; + reg = <0x1004ec00 0x400>; + interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "alarm", "period", "carry"; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattclk VBATTB_VBATTCLK>; + clock-names = "bus", "counter"; + assigned-clocks = <&vbattb VBATTB_MUX>; + assigned-clock-parents = <&vbattb VBATTB_XC>; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + };