| Message ID | 20240820103756.3545976-1-maz@kernel.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | KVM: arm64: nv: Add support for address translation instructions | expand |
Hi Marc, On 20-08-2024 04:07 pm, Marc Zyngier wrote: > This is the fourth revision of the address translation emulation for > NV support on arm64 previously posted at [1]. > > Thanks again to Alex for his continuous (contiguous? ;-) scrutiny on > this series. > > * From v3: > > - Fix out of range conditions for TxSZ when LVA is implemented > > - Fix implementation of R_VPBBF to deliver an Address Size Fault > > - Don't grant PX if UW is set > > - Various cleanups > > - Collected Alex's RBs, with thanks. > > I've added the usual reviewers on Cc, plus people who explicitly asked > to be on it, and people who seem to be super keen on NV. > > Patches on top of 6.11-rc1, tested on my usual M2 (so VHE only). FWIW, > I plan to take this into 6.12. > > [1] https://lore.kernel.org/r/20240813100540.1955263-1-maz@kernel.org > > Joey Gouly (1): > KVM: arm64: Make kvm_at() take an OP_AT_* > Have you tested/tried NV with host/L0 booted with GICv4.x enabled? We do see L2 boot hang and I don't have much debug info at the moment. > Marc Zyngier (17): > arm64: Add missing APTable and TCR_ELx.HPD masks > arm64: Add PAR_EL1 field description > arm64: Add system register encoding for PSTATE.PAN > arm64: Add ESR_ELx_FSC_ADDRSZ_L() helper > KVM: arm64: nv: Enforce S2 alignment when contiguous bit is set > KVM: arm64: nv: Turn upper_attr for S2 walk into the full descriptor > KVM: arm64: nv: Honor absence of FEAT_PAN2 > KVM: arm64: nv: Add basic emulation of AT S1E{0,1}{R,W} > KVM: arm64: nv: Add basic emulation of AT S1E1{R,W}P > KVM: arm64: nv: Add basic emulation of AT S1E2{R,W} > KVM: arm64: nv: Add emulation of AT S12E{0,1}{R,W} > KVM: arm64: nv: Make ps_to_output_size() generally available > KVM: arm64: nv: Add SW walker for AT S1 emulation > KVM: arm64: nv: Sanitise SCTLR_EL1.EPAN according to VM configuration > KVM: arm64: nv: Make AT+PAN instructions aware of FEAT_PAN3 > KVM: arm64: nv: Plumb handling of AT S1* traps from EL2 > KVM: arm64: nv: Add support for FEAT_ATS1A > > arch/arm64/include/asm/esr.h | 5 +- > arch/arm64/include/asm/kvm_arm.h | 1 + > arch/arm64/include/asm/kvm_asm.h | 6 +- > arch/arm64/include/asm/kvm_nested.h | 40 +- > arch/arm64/include/asm/pgtable-hwdef.h | 9 + > arch/arm64/include/asm/sysreg.h | 22 + > arch/arm64/kvm/Makefile | 2 +- > arch/arm64/kvm/at.c | 1101 ++++++++++++++++++++++++ > arch/arm64/kvm/emulate-nested.c | 2 + > arch/arm64/kvm/hyp/include/hyp/fault.h | 2 +- > arch/arm64/kvm/nested.c | 41 +- > arch/arm64/kvm/sys_regs.c | 60 ++ > 12 files changed, 1259 insertions(+), 32 deletions(-) > create mode 100644 arch/arm64/kvm/at.c >
Hi Ganapat, On Wed, Aug 21, 2024 at 09:55:37AM +0530, Ganapatrao Kulkarni wrote: > Have you tested/tried NV with host/L0 booted with GICv4.x enabled? > We do see L2 boot hang and I don't have much debug info at the moment. Sorry, I've been sitting on a fix for this that I've been meaning to send out. The issue has to do with the fact that the vpe is marked as runnable (its_vpe::pending_last = true) when descheduled w/o requesting a doorbell IRQ. Once KVM completes the nested ERET, it believes an IRQ is pending for L1 (kvm_vgic_vcpu_pending_irq() returns true), and injects the nested exception. This can be papered over by requesting the doorbell IRQ, which we need anyway to kick us out of the L2 when an IRQ becomes pending for L1. Could you take this diff for a spin? diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 0ae093bae054..9d07184d79b1 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -613,6 +613,12 @@ struct cpu_sve_state { * field. */ struct kvm_host_data { + /* SVE enabled for EL0 */ +#define HOST_SVE_ENABLED 0 + /* SME enabled for EL0 */ +#define HOST_SME_ENABLED 1 + unsigned long flags; + struct kvm_cpu_context host_ctxt; /* @@ -908,10 +914,8 @@ struct kvm_vcpu_arch { /* Save TRBE context if active */ #define DEBUG_STATE_SAVE_TRBE __vcpu_single_flag(iflags, BIT(6)) -/* SVE enabled for host EL0 */ -#define HOST_SVE_ENABLED __vcpu_single_flag(sflags, BIT(0)) -/* SME enabled for EL0 */ -#define HOST_SME_ENABLED __vcpu_single_flag(sflags, BIT(1)) +/* KVM is currently emulating a nested ERET */ +#define IN_NESTED_ERET __vcpu_single_flag(sflags, BIT(0)) /* Physical CPU not in supported_cpus */ #define ON_UNSUPPORTED_CPU __vcpu_single_flag(sflags, BIT(2)) /* WFIT instruction trapped */ @@ -1294,6 +1298,10 @@ DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data); &this_cpu_ptr_hyp_sym(kvm_host_data)->f) #endif +#define host_data_set_flag(nr) set_bit(nr, host_data_ptr(flags)) +#define host_data_test_flag(nr) test_bit(nr, host_data_ptr(flags)) +#define host_data_clear_flag(nr) clear_bit(nr, host_data_ptr(flags)) + /* Check whether the FP regs are owned by the guest */ static inline bool guest_owns_fp_regs(void) { diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c index 05166eccea0a..fd3d6275b777 100644 --- a/arch/arm64/kvm/emulate-nested.c +++ b/arch/arm64/kvm/emulate-nested.c @@ -2310,6 +2310,7 @@ void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu) } preempt_disable(); + vcpu_set_flag(vcpu, IN_NESTED_ERET); kvm_arch_vcpu_put(vcpu); if (!esr_iss_is_eretax(esr)) @@ -2321,6 +2322,7 @@ void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu) *vcpu_cpsr(vcpu) = spsr; kvm_arch_vcpu_load(vcpu, smp_processor_id()); + vcpu_clear_flag(vcpu, IN_NESTED_ERET); preempt_enable(); } diff --git a/arch/arm64/kvm/fpsimd.c b/arch/arm64/kvm/fpsimd.c index c53e5b14038d..f7712c89adef 100644 --- a/arch/arm64/kvm/fpsimd.c +++ b/arch/arm64/kvm/fpsimd.c @@ -64,14 +64,14 @@ void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu) *host_data_ptr(fp_owner) = FP_STATE_HOST_OWNED; *host_data_ptr(fpsimd_state) = kern_hyp_va(¤t->thread.uw.fpsimd_state); - vcpu_clear_flag(vcpu, HOST_SVE_ENABLED); + host_data_clear_flag(HOST_SVE_ENABLED); if (read_sysreg(cpacr_el1) & CPACR_EL1_ZEN_EL0EN) - vcpu_set_flag(vcpu, HOST_SVE_ENABLED); + host_data_set_flag(HOST_SVE_ENABLED); if (system_supports_sme()) { - vcpu_clear_flag(vcpu, HOST_SME_ENABLED); + host_data_clear_flag(HOST_SME_ENABLED); if (read_sysreg(cpacr_el1) & CPACR_EL1_SMEN_EL0EN) - vcpu_set_flag(vcpu, HOST_SME_ENABLED); + host_data_set_flag(HOST_SME_ENABLED); /* * If PSTATE.SM is enabled then save any pending FP @@ -167,7 +167,7 @@ void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu) */ if (has_vhe() && system_supports_sme()) { /* Also restore EL0 state seen on entry */ - if (vcpu_get_flag(vcpu, HOST_SME_ENABLED)) + if (host_data_test_flag(HOST_SME_ENABLED)) sysreg_clear_set(CPACR_EL1, 0, CPACR_ELx_SMEN); else sysreg_clear_set(CPACR_EL1, @@ -226,7 +226,7 @@ void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu) * for EL0. To avoid spurious traps, restore the trap state * seen by kvm_arch_vcpu_load_fp(): */ - if (vcpu_get_flag(vcpu, HOST_SVE_ENABLED)) + if (host_data_test_flag(HOST_SVE_ENABLED)) sysreg_clear_set(CPACR_EL1, 0, CPACR_EL1_ZEN_EL0EN); else sysreg_clear_set(CPACR_EL1, CPACR_EL1_ZEN_EL0EN, 0); diff --git a/arch/arm64/kvm/vgic/vgic-v4.c b/arch/arm64/kvm/vgic/vgic-v4.c index 74a67ad87f29..9f3f06ac76cc 100644 --- a/arch/arm64/kvm/vgic/vgic-v4.c +++ b/arch/arm64/kvm/vgic/vgic-v4.c @@ -336,6 +336,22 @@ void vgic_v4_teardown(struct kvm *kvm) its_vm->vpes = NULL; } +static inline bool vgic_v4_want_doorbell(struct kvm_vcpu *vcpu) +{ + if (vcpu_get_flag(vcpu, IN_WFI)) + return true; + + if (likely(!vcpu_has_nv(vcpu))) + return false; + + /* + * GICv4 hardware is only ever used for the L1. Mark the vPE (i.e. the + * L1 context) nonresident and request a doorbell to kick us out of the + * L2 when an IRQ becomes pending. + */ + return vcpu_get_flag(vcpu, IN_NESTED_ERET); +} + int vgic_v4_put(struct kvm_vcpu *vcpu) { struct its_vpe *vpe = &vcpu->arch.vgic_cpu.vgic_v3.its_vpe; @@ -343,7 +359,7 @@ int vgic_v4_put(struct kvm_vcpu *vcpu) if (!vgic_supports_direct_msis(vcpu->kvm) || !vpe->resident) return 0; - return its_make_vpe_non_resident(vpe, !!vcpu_get_flag(vcpu, IN_WFI)); + return its_make_vpe_non_resident(vpe, vgic_v4_want_doorbell(vcpu)); } int vgic_v4_load(struct kvm_vcpu *vcpu)
On 21-08-2024 12:32 pm, Oliver Upton wrote: > Hi Ganapat, > > On Wed, Aug 21, 2024 at 09:55:37AM +0530, Ganapatrao Kulkarni wrote: >> Have you tested/tried NV with host/L0 booted with GICv4.x enabled? >> We do see L2 boot hang and I don't have much debug info at the moment. > > Sorry, I've been sitting on a fix for this that I've been meaning to > send out. > > The issue has to do with the fact that the vpe is marked as runnable > (its_vpe::pending_last = true) when descheduled w/o requesting a > doorbell IRQ. Once KVM completes the nested ERET, it believes an IRQ is > pending for L1 (kvm_vgic_vcpu_pending_irq() returns true), and injects > the nested exception. Ah OK, I could see it was returning back to L1 after ERET in ftrace and this was getting in loop and L2 was never getting a chance to run. > > This can be papered over by requesting the doorbell IRQ, which we need > anyway to kick us out of the L2 when an IRQ becomes pending for L1. > > Could you take this diff for a spin? Thanks Oliver for this fix!. I could boot L1 and then L2 with this diff. > > diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h > index 0ae093bae054..9d07184d79b1 100644 > --- a/arch/arm64/include/asm/kvm_host.h > +++ b/arch/arm64/include/asm/kvm_host.h > @@ -613,6 +613,12 @@ struct cpu_sve_state { > * field. > */ > struct kvm_host_data { > + /* SVE enabled for EL0 */ > +#define HOST_SVE_ENABLED 0 > + /* SME enabled for EL0 */ > +#define HOST_SME_ENABLED 1 > + unsigned long flags; > + > struct kvm_cpu_context host_ctxt; > > /* > @@ -908,10 +914,8 @@ struct kvm_vcpu_arch { > /* Save TRBE context if active */ > #define DEBUG_STATE_SAVE_TRBE __vcpu_single_flag(iflags, BIT(6)) > > -/* SVE enabled for host EL0 */ > -#define HOST_SVE_ENABLED __vcpu_single_flag(sflags, BIT(0)) > -/* SME enabled for EL0 */ > -#define HOST_SME_ENABLED __vcpu_single_flag(sflags, BIT(1)) > +/* KVM is currently emulating a nested ERET */ > +#define IN_NESTED_ERET __vcpu_single_flag(sflags, BIT(0)) > /* Physical CPU not in supported_cpus */ > #define ON_UNSUPPORTED_CPU __vcpu_single_flag(sflags, BIT(2)) > /* WFIT instruction trapped */ > @@ -1294,6 +1298,10 @@ DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data); > &this_cpu_ptr_hyp_sym(kvm_host_data)->f) > #endif > > +#define host_data_set_flag(nr) set_bit(nr, host_data_ptr(flags)) > +#define host_data_test_flag(nr) test_bit(nr, host_data_ptr(flags)) > +#define host_data_clear_flag(nr) clear_bit(nr, host_data_ptr(flags)) > + > /* Check whether the FP regs are owned by the guest */ > static inline bool guest_owns_fp_regs(void) > { > diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c > index 05166eccea0a..fd3d6275b777 100644 > --- a/arch/arm64/kvm/emulate-nested.c > +++ b/arch/arm64/kvm/emulate-nested.c > @@ -2310,6 +2310,7 @@ void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu) > } > > preempt_disable(); > + vcpu_set_flag(vcpu, IN_NESTED_ERET); > kvm_arch_vcpu_put(vcpu); > > if (!esr_iss_is_eretax(esr)) > @@ -2321,6 +2322,7 @@ void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu) > *vcpu_cpsr(vcpu) = spsr; > > kvm_arch_vcpu_load(vcpu, smp_processor_id()); > + vcpu_clear_flag(vcpu, IN_NESTED_ERET); > preempt_enable(); > } > > diff --git a/arch/arm64/kvm/fpsimd.c b/arch/arm64/kvm/fpsimd.c > index c53e5b14038d..f7712c89adef 100644 > --- a/arch/arm64/kvm/fpsimd.c > +++ b/arch/arm64/kvm/fpsimd.c > @@ -64,14 +64,14 @@ void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu) > *host_data_ptr(fp_owner) = FP_STATE_HOST_OWNED; > *host_data_ptr(fpsimd_state) = kern_hyp_va(¤t->thread.uw.fpsimd_state); > > - vcpu_clear_flag(vcpu, HOST_SVE_ENABLED); > + host_data_clear_flag(HOST_SVE_ENABLED); > if (read_sysreg(cpacr_el1) & CPACR_EL1_ZEN_EL0EN) > - vcpu_set_flag(vcpu, HOST_SVE_ENABLED); > + host_data_set_flag(HOST_SVE_ENABLED); > > if (system_supports_sme()) { > - vcpu_clear_flag(vcpu, HOST_SME_ENABLED); > + host_data_clear_flag(HOST_SME_ENABLED); > if (read_sysreg(cpacr_el1) & CPACR_EL1_SMEN_EL0EN) > - vcpu_set_flag(vcpu, HOST_SME_ENABLED); > + host_data_set_flag(HOST_SME_ENABLED); > > /* > * If PSTATE.SM is enabled then save any pending FP > @@ -167,7 +167,7 @@ void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu) > */ > if (has_vhe() && system_supports_sme()) { > /* Also restore EL0 state seen on entry */ > - if (vcpu_get_flag(vcpu, HOST_SME_ENABLED)) > + if (host_data_test_flag(HOST_SME_ENABLED)) > sysreg_clear_set(CPACR_EL1, 0, CPACR_ELx_SMEN); > else > sysreg_clear_set(CPACR_EL1, > @@ -226,7 +226,7 @@ void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu) > * for EL0. To avoid spurious traps, restore the trap state > * seen by kvm_arch_vcpu_load_fp(): > */ > - if (vcpu_get_flag(vcpu, HOST_SVE_ENABLED)) > + if (host_data_test_flag(HOST_SVE_ENABLED)) > sysreg_clear_set(CPACR_EL1, 0, CPACR_EL1_ZEN_EL0EN); > else > sysreg_clear_set(CPACR_EL1, CPACR_EL1_ZEN_EL0EN, 0); > diff --git a/arch/arm64/kvm/vgic/vgic-v4.c b/arch/arm64/kvm/vgic/vgic-v4.c > index 74a67ad87f29..9f3f06ac76cc 100644 > --- a/arch/arm64/kvm/vgic/vgic-v4.c > +++ b/arch/arm64/kvm/vgic/vgic-v4.c > @@ -336,6 +336,22 @@ void vgic_v4_teardown(struct kvm *kvm) > its_vm->vpes = NULL; > } > > +static inline bool vgic_v4_want_doorbell(struct kvm_vcpu *vcpu) > +{ > + if (vcpu_get_flag(vcpu, IN_WFI)) > + return true; > + > + if (likely(!vcpu_has_nv(vcpu))) > + return false; > + > + /* > + * GICv4 hardware is only ever used for the L1. Mark the vPE (i.e. the > + * L1 context) nonresident and request a doorbell to kick us out of the > + * L2 when an IRQ becomes pending. > + */ > + return vcpu_get_flag(vcpu, IN_NESTED_ERET); > +} > + > int vgic_v4_put(struct kvm_vcpu *vcpu) > { > struct its_vpe *vpe = &vcpu->arch.vgic_cpu.vgic_v3.its_vpe; > @@ -343,7 +359,7 @@ int vgic_v4_put(struct kvm_vcpu *vcpu) > if (!vgic_supports_direct_msis(vcpu->kvm) || !vpe->resident) > return 0; > > - return its_make_vpe_non_resident(vpe, !!vcpu_get_flag(vcpu, IN_WFI)); > + return its_make_vpe_non_resident(vpe, vgic_v4_want_doorbell(vcpu)); > } > > int vgic_v4_load(struct kvm_vcpu *vcpu) >
On Tue, 20 Aug 2024 11:37:38 +0100, Marc Zyngier wrote: > This is the fourth revision of the address translation emulation for > NV support on arm64 previously posted at [1]. > > Thanks again to Alex for his continuous (contiguous? ;-) scrutiny on > this series. > > * From v3: > > [...] Applied to kvm-arm64/s2-ptdump, thanks! [01/18] arm64: Add missing APTable and TCR_ELx.HPD masks commit: 4abc783e4741cd33216e7796e9b2f4973b4bca61 [02/18] arm64: Add PAR_EL1 field description commit: 6dcd2ac7ea7c5b20b416ee09d8d5d2ec89866ef8 [03/18] arm64: Add system register encoding for PSTATE.PAN commit: b229b46b0bf7828bef5f88c91708776869b751ac [04/18] arm64: Add ESR_ELx_FSC_ADDRSZ_L() helper commit: 5fddf9abc31a57e2cc35287998994cf4a684fada [05/18] KVM: arm64: Make kvm_at() take an OP_AT_* commit: 69231a6fcb638b7929e9fc88c4fa73a04e6d4e0c [06/18] KVM: arm64: nv: Enforce S2 alignment when contiguous bit is set commit: 4155539bc5baab514ac71285a1a13fcf148f9cf1 [07/18] KVM: arm64: nv: Turn upper_attr for S2 walk into the full descriptor commit: 0a0f25b71ca544388717f8bf4a54ba324e234e7a [08/18] KVM: arm64: nv: Honor absence of FEAT_PAN2 commit: 90659853febcf63ceb71529b247d518df3c2a76c [09/18] KVM: arm64: nv: Add basic emulation of AT S1E{0,1}{R,W} commit: 477e89cabb1428d5989430d57828347f5de2be9c [10/18] KVM: arm64: nv: Add basic emulation of AT S1E1{R,W}P commit: be0135bde1df5e80cffacd2ed6f952e6d38d6f71 [11/18] KVM: arm64: nv: Add basic emulation of AT S1E2{R,W} commit: e794049b9acbd6500b77b9ce92a95101091b52d3 [12/18] KVM: arm64: nv: Add emulation of AT S12E{0,1}{R,W} commit: be04cebf3e78874627dc1042991d5d504464a5cc [13/18] KVM: arm64: nv: Make ps_to_output_size() generally available commit: 97634dac1974d28e5ffc067d257f0b0f79b5ed2e [14/18] KVM: arm64: nv: Add SW walker for AT S1 emulation commit: d6a01a2dc760c8350fa182a6afd69fabab131f73 [15/18] KVM: arm64: nv: Sanitise SCTLR_EL1.EPAN according to VM configuration commit: 2441418f3aadb3f9232431aeb10d89e48a934d94 [16/18] KVM: arm64: nv: Make AT+PAN instructions aware of FEAT_PAN3 commit: d95bb9ef164edb33565cb73e3f0b0a581b3e4fbb [17/18] KVM: arm64: nv: Plumb handling of AT S1* traps from EL2 commit: 8df747f4f3a5c680e3c0e68af3487b97343ca80a [18/18] KVM: arm64: nv: Add support for FEAT_ATS1A commit: ff987ffc0c18c98f05ddc7696d56bb493b994450 Cheers, M.
On Fri, 30 Aug 2024 21:01:24 +0100, Marc Zyngier <maz@kernel.org> wrote: > > On Tue, 20 Aug 2024 11:37:38 +0100, Marc Zyngier wrote: > > This is the fourth revision of the address translation emulation for > > NV support on arm64 previously posted at [1]. > > > > Thanks again to Alex for his continuous (contiguous? ;-) scrutiny on > > this series. > > > > * From v3: > > > > [...] > > Applied to kvm-arm64/s2-ptdump, thanks! Note to self: fix the bloody script so that it reports -next and whatever branch I'm currently working on. M.
This is the fourth revision of the address translation emulation for NV support on arm64 previously posted at [1]. Thanks again to Alex for his continuous (contiguous? ;-) scrutiny on this series. * From v3: - Fix out of range conditions for TxSZ when LVA is implemented - Fix implementation of R_VPBBF to deliver an Address Size Fault - Don't grant PX if UW is set - Various cleanups - Collected Alex's RBs, with thanks. I've added the usual reviewers on Cc, plus people who explicitly asked to be on it, and people who seem to be super keen on NV. Patches on top of 6.11-rc1, tested on my usual M2 (so VHE only). FWIW, I plan to take this into 6.12. [1] https://lore.kernel.org/r/20240813100540.1955263-1-maz@kernel.org Joey Gouly (1): KVM: arm64: Make kvm_at() take an OP_AT_* Marc Zyngier (17): arm64: Add missing APTable and TCR_ELx.HPD masks arm64: Add PAR_EL1 field description arm64: Add system register encoding for PSTATE.PAN arm64: Add ESR_ELx_FSC_ADDRSZ_L() helper KVM: arm64: nv: Enforce S2 alignment when contiguous bit is set KVM: arm64: nv: Turn upper_attr for S2 walk into the full descriptor KVM: arm64: nv: Honor absence of FEAT_PAN2 KVM: arm64: nv: Add basic emulation of AT S1E{0,1}{R,W} KVM: arm64: nv: Add basic emulation of AT S1E1{R,W}P KVM: arm64: nv: Add basic emulation of AT S1E2{R,W} KVM: arm64: nv: Add emulation of AT S12E{0,1}{R,W} KVM: arm64: nv: Make ps_to_output_size() generally available KVM: arm64: nv: Add SW walker for AT S1 emulation KVM: arm64: nv: Sanitise SCTLR_EL1.EPAN according to VM configuration KVM: arm64: nv: Make AT+PAN instructions aware of FEAT_PAN3 KVM: arm64: nv: Plumb handling of AT S1* traps from EL2 KVM: arm64: nv: Add support for FEAT_ATS1A arch/arm64/include/asm/esr.h | 5 +- arch/arm64/include/asm/kvm_arm.h | 1 + arch/arm64/include/asm/kvm_asm.h | 6 +- arch/arm64/include/asm/kvm_nested.h | 40 +- arch/arm64/include/asm/pgtable-hwdef.h | 9 + arch/arm64/include/asm/sysreg.h | 22 + arch/arm64/kvm/Makefile | 2 +- arch/arm64/kvm/at.c | 1101 ++++++++++++++++++++++++ arch/arm64/kvm/emulate-nested.c | 2 + arch/arm64/kvm/hyp/include/hyp/fault.h | 2 +- arch/arm64/kvm/nested.c | 41 +- arch/arm64/kvm/sys_regs.c | 60 ++ 12 files changed, 1259 insertions(+), 32 deletions(-) create mode 100644 arch/arm64/kvm/at.c