new file mode 100644
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,ipq5332-nsscc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ5332
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+
+description: |
+ Qualcomm networking sub system clock control module provides the clocks,
+ resets and power domains on IPQ5332
+
+ See also::
+ include/dt-bindings/clock/qcom,ipq5332-nsscc.h
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+properties:
+ compatible:
+ const: qcom,ipq5332-nsscc
+
+ clocks:
+ items:
+ - description: Common PLL nss clock 200M source
+ - description: Common PLL nss clock 300M source
+ - description: GCC GPLL0 out aux clock source
+ - description: Uniphy0 NSS Rx clock source
+ - description: Uniphy0 NSS Tx clock source
+ - description: Uniphy1 NSS Rx clock source
+ - description: Uniphy1 NSS Tx clock source
+ - description: Board XO source
+
+ '#power-domain-cells': false
+ '#interconnect-cells':
+ const: 1
+
+required:
+ - compatible
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ clock-controller@39b00000 {
+ compatible = "qcom,ipq5332-nsscc";
+ reg = <0x39b00000 0x80000>;
+ clocks = <&bias_pll_cc_clk>,
+ <&bias_pll_nss_noc_clk>,
+ <&gcc_gpll0_out_aux>,
+ <&uniphy 0>,
+ <&uniphy 1>,
+ <&uniphy 2>,
+ <&uniphy 3>,
+ <&xo_board_clk>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #interconnect-cells = <1>;
+ };
+...
new file mode 100644
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_NSS_CC_IPQ5332_H
+#define _DT_BINDINGS_CLK_QCOM_NSS_CC_IPQ5332_H
+
+/* NSS_CC clocks */
+#define NSS_CC_CE_APB_CLK 0
+#define NSS_CC_CE_AXI_CLK 1
+#define NSS_CC_CE_CLK_SRC 2
+#define NSS_CC_CFG_CLK_SRC 3
+#define NSS_CC_DEBUG_CLK 4
+#define NSS_CC_EIP_BFDCD_CLK_SRC 5
+#define NSS_CC_EIP_CLK 6
+#define NSS_CC_NSS_CSR_CLK 7
+#define NSS_CC_NSSNOC_CE_APB_CLK 8
+#define NSS_CC_NSSNOC_CE_AXI_CLK 9
+#define NSS_CC_NSSNOC_EIP_CLK 10
+#define NSS_CC_NSSNOC_NSS_CSR_CLK 11
+#define NSS_CC_NSSNOC_PPE_CFG_CLK 12
+#define NSS_CC_NSSNOC_PPE_CLK 13
+#define NSS_CC_PORT1_MAC_CLK 14
+#define NSS_CC_PORT1_RX_CLK 15
+#define NSS_CC_PORT1_RX_CLK_SRC 16
+#define NSS_CC_PORT1_RX_DIV_CLK_SRC 17
+#define NSS_CC_PORT1_TX_CLK 18
+#define NSS_CC_PORT1_TX_CLK_SRC 19
+#define NSS_CC_PORT1_TX_DIV_CLK_SRC 20
+#define NSS_CC_PORT2_MAC_CLK 21
+#define NSS_CC_PORT2_RX_CLK 22
+#define NSS_CC_PORT2_RX_CLK_SRC 23
+#define NSS_CC_PORT2_RX_DIV_CLK_SRC 24
+#define NSS_CC_PORT2_TX_CLK 25
+#define NSS_CC_PORT2_TX_CLK_SRC 26
+#define NSS_CC_PORT2_TX_DIV_CLK_SRC 27
+#define NSS_CC_PPE_CLK_SRC 28
+#define NSS_CC_PPE_EDMA_CFG_CLK 29
+#define NSS_CC_PPE_EDMA_CLK 30
+#define NSS_CC_PPE_SWITCH_BTQ_CLK 31
+#define NSS_CC_PPE_SWITCH_CFG_CLK 32
+#define NSS_CC_PPE_SWITCH_CLK 33
+#define NSS_CC_PPE_SWITCH_IPE_CLK 34
+#define NSS_CC_UNIPHY_PORT1_RX_CLK 35
+#define NSS_CC_UNIPHY_PORT1_TX_CLK 36
+#define NSS_CC_UNIPHY_PORT2_RX_CLK 37
+#define NSS_CC_UNIPHY_PORT2_TX_CLK 38
+#define NSS_CC_XGMAC0_PTP_REF_CLK 39
+#define NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC 40
+#define NSS_CC_XGMAC1_PTP_REF_CLK 41
+#define NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC 42
+
+#define NSS_CC_CE_APB_CLK_ARES 0
+#define NSS_CC_CE_AXI_CLK_ARES 1
+#define NSS_CC_DEBUG_CLK_ARES 2
+#define NSS_CC_EIP_CLK_ARES 3
+#define NSS_CC_NSS_CSR_CLK_ARES 4
+#define NSS_CC_NSSNOC_CE_APB_CLK_ARES 5
+#define NSS_CC_NSSNOC_CE_AXI_CLK_ARES 6
+#define NSS_CC_NSSNOC_EIP_CLK_ARES 7
+#define NSS_CC_NSSNOC_NSS_CSR_CLK_ARES 8
+#define NSS_CC_NSSNOC_PPE_CLK_ARES 9
+#define NSS_CC_NSSNOC_PPE_CFG_CLK_ARES 10
+#define NSS_CC_PORT1_MAC_CLK_ARES 11
+#define NSS_CC_PORT1_RX_CLK_ARES 12
+#define NSS_CC_PORT1_TX_CLK_ARES 13
+#define NSS_CC_PORT2_MAC_CLK_ARES 14
+#define NSS_CC_PORT2_RX_CLK_ARES 15
+#define NSS_CC_PORT2_TX_CLK_ARES 16
+#define NSS_CC_PPE_BCR 17
+#define NSS_CC_PPE_EDMA_CLK_ARES 18
+#define NSS_CC_PPE_EDMA_CFG_CLK_ARES 19
+#define NSS_CC_PPE_SWITCH_BTQ_CLK_ARES 20
+#define NSS_CC_PPE_SWITCH_CLK_ARES 21
+#define NSS_CC_PPE_SWITCH_CFG_CLK_ARES 22
+#define NSS_CC_PPE_SWITCH_IPE_CLK_ARES 23
+#define NSS_CC_UNIPHY_PORT1_RX_CLK_ARES 24
+#define NSS_CC_UNIPHY_PORT1_TX_CLK_ARES 25
+#define NSS_CC_UNIPHY_PORT2_RX_CLK_ARES 26
+#define NSS_CC_UNIPHY_PORT2_TX_CLK_ARES 27
+#define NSS_CC_XGMAC0_PTP_REF_CLK_ARES 28
+#define NSS_CC_XGMAC1_PTP_REF_CLK_ARES 29
+
+#endif