[v3,01/12] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB

Commit Message

Claudiu Beznea Aug. 30, 2024, 1:02 p.m. UTC

From: Claudiu Beznea <[e-mail]>

The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC,
the tamper detector and a small general usage memory of 128B. Add
documentation for it.

Signed-off-by: Claudiu Beznea <[e-mail]>
---

Changes in v3:
- moved the file to clock dt bindings directory as it is the
  only functionality supported at the moment; the other functionalities
  (tamper detector, SRAM) are offered though register spreaded
  though the address space of the VBATTB IP and not actually
  individual devices; the other functionalities are not
  planned to be supported soon and if they will be I think they
  fit better on auxiliary bus than MFD
- dropped interrupt names as requested in the review process
- dropped the inner node for clock controller
- added #clock-cells
- added rtx clock
- updated description for renesas,vbattb-load-nanofarads
- included dt-bindings/interrupt-controller/irq.h in examples section

Changes in v2:
- changed file name and compatible
- updated title, description sections
- added clock controller part documentation and drop dedicated file
  for it included in v1
- used items to describe interrupts, interrupt-names, clocks, clock-names,
  resets
- dropped node labels and status
- updated clock-names for clock controller to cope with the new
  logic on detecting the necessity to setup bypass

 .../clock/renesas,r9a08g045-vbattb.yaml       | 81 +++++++++++++++++++
 1 file changed, 81 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml

Comments

Rob Herring Aug. 30, 2024, 5:46 p.m. UTC | #1

On Fri, Aug 30, 2024 at 04:02:07PM +0300, Claudiu wrote:
> From: Claudiu Beznea <[e-mail]>
> 
> The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC,
> the tamper detector and a small general usage memory of 128B. Add
> documentation for it.
> 
> Signed-off-by: Claudiu Beznea <[e-mail]>
> ---
> 
> Changes in v3:
> - moved the file to clock dt bindings directory as it is the
>   only functionality supported at the moment; the other functionalities
>   (tamper detector, SRAM) are offered though register spreaded
>   though the address space of the VBATTB IP and not actually
>   individual devices; the other functionalities are not
>   planned to be supported soon and if they will be I think they
>   fit better on auxiliary bus than MFD
> - dropped interrupt names as requested in the review process
> - dropped the inner node for clock controller
> - added #clock-cells
> - added rtx clock
> - updated description for renesas,vbattb-load-nanofarads
> - included dt-bindings/interrupt-controller/irq.h in examples section
> 
> Changes in v2:
> - changed file name and compatible
> - updated title, description sections
> - added clock controller part documentation and drop dedicated file
>   for it included in v1
> - used items to describe interrupts, interrupt-names, clocks, clock-names,
>   resets
> - dropped node labels and status
> - updated clock-names for clock controller to cope with the new
>   logic on detecting the necessity to setup bypass
> 
>  .../clock/renesas,r9a08g045-vbattb.yaml       | 81 +++++++++++++++++++
>  1 file changed, 81 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml
> 
> diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml
> new file mode 100644
> index 000000000000..29df0e01fae5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml
> @@ -0,0 +1,81 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/renesas,r9a08g045-vbattb.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas Battery Backup Function (VBATTB)
> +
> +description:
> +  Renesas VBATTB is an always on powered module (backed by battery) which
> +  controls the RTC clock (VBATTCLK), tamper detection logic and a small
> +  general usage memory (128B).
> +
> +maintainers:
> +  - Claudiu Beznea <[e-mail]>
> +
> +properties:
> +  compatible:
> +    const: renesas,r9a08g045-vbattb
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    items:
> +      - description: tamper detector interrupt
> +
> +  clocks:
> +    items:
> +      - description: VBATTB module clock
> +      - description: RTC input clock (crystal oscillator or external clock device)
> +
> +  clock-names:
> +    items:
> +      - const: bclk
> +      - const: rtx
> +
> +  '#clock-cells':
> +    const: 1
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  resets:
> +    items:
> +      - description: VBATTB module reset
> +
> +  renesas,vbattb-load-nanofarads:

Use defined units, don't add your own. So -picofarads should work for 
you.

> +    description: load capacitance of the on board crystal oscillator
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [ 4000, 7000, 9000, 12500 ]
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - clocks
> +  - clock-names
> +  - '#clock-cells'
> +  - power-domains
> +  - resets
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/r9a08g045-cpg.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +
> +    vbattb@1005c000 {

clock-controller@...

> +        compatible = "renesas,r9a08g045-vbattb";
> +        reg = <0x1005c000 0x1000>;
> +        interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> +        clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
> +        clock-names = "bclk", "rtx";
> +        #clock-cells = <1>;
> +        power-domains = <&cpg>;
> +        resets = <&cpg R9A08G045_VBAT_BRESETN>;
> +        renesas,vbattb-load-nanofarads = <12500>;
> +    };
> -- 
> 2.39.2
>

Alexandre Belloni Aug. 30, 2024, 10:06 p.m. UTC | #2

On 30/08/2024 12:46:33-0500, Rob Herring wrote:
> On Fri, Aug 30, 2024 at 04:02:07PM +0300, Claudiu wrote:
> > From: Claudiu Beznea <[e-mail]>
> > 
> > The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC,
> > the tamper detector and a small general usage memory of 128B. Add
> > documentation for it.
> > 
> > Signed-off-by: Claudiu Beznea <[e-mail]>
> > ---
> > 
> > Changes in v3:
> > - moved the file to clock dt bindings directory as it is the
> >   only functionality supported at the moment; the other functionalities
> >   (tamper detector, SRAM) are offered though register spreaded
> >   though the address space of the VBATTB IP and not actually
> >   individual devices; the other functionalities are not
> >   planned to be supported soon and if they will be I think they
> >   fit better on auxiliary bus than MFD
> > - dropped interrupt names as requested in the review process
> > - dropped the inner node for clock controller
> > - added #clock-cells
> > - added rtx clock
> > - updated description for renesas,vbattb-load-nanofarads
> > - included dt-bindings/interrupt-controller/irq.h in examples section
> > 
> > Changes in v2:
> > - changed file name and compatible
> > - updated title, description sections
> > - added clock controller part documentation and drop dedicated file
> >   for it included in v1
> > - used items to describe interrupts, interrupt-names, clocks, clock-names,
> >   resets
> > - dropped node labels and status
> > - updated clock-names for clock controller to cope with the new
> >   logic on detecting the necessity to setup bypass
> > 
> >  .../clock/renesas,r9a08g045-vbattb.yaml       | 81 +++++++++++++++++++
> >  1 file changed, 81 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml
> > new file mode 100644
> > index 000000000000..29df0e01fae5
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml
> > @@ -0,0 +1,81 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/renesas,r9a08g045-vbattb.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Renesas Battery Backup Function (VBATTB)
> > +
> > +description:
> > +  Renesas VBATTB is an always on powered module (backed by battery) which
> > +  controls the RTC clock (VBATTCLK), tamper detection logic and a small
> > +  general usage memory (128B).
> > +
> > +maintainers:
> > +  - Claudiu Beznea <[e-mail]>
> > +
> > +properties:
> > +  compatible:
> > +    const: renesas,r9a08g045-vbattb
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    items:
> > +      - description: tamper detector interrupt
> > +
> > +  clocks:
> > +    items:
> > +      - description: VBATTB module clock
> > +      - description: RTC input clock (crystal oscillator or external clock device)
> > +
> > +  clock-names:
> > +    items:
> > +      - const: bclk
> > +      - const: rtx
> > +
> > +  '#clock-cells':
> > +    const: 1
> > +
> > +  power-domains:
> > +    maxItems: 1
> > +
> > +  resets:
> > +    items:
> > +      - description: VBATTB module reset
> > +
> > +  renesas,vbattb-load-nanofarads:
> 
> Use defined units, don't add your own. So -picofarads should work for 
> you.

We have a generic quartz-load-femtofarads property for RTCs which is
what you define because the driver has VBATTB_XOSCCR_XSEL_4_PF which I
guess is 4 pF which is 0.004 nF and 4000 fF.

> 
> > +    description: load capacitance of the on board crystal oscillator
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    enum: [ 4000, 7000, 9000, 12500 ]
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - clocks
> > +  - clock-names
> > +  - '#clock-cells'
> > +  - power-domains
> > +  - resets
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/clock/r9a08g045-cpg.h>
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +    #include <dt-bindings/interrupt-controller/irq.h>
> > +
> > +    vbattb@1005c000 {
> 
> clock-controller@...
> 
> > +        compatible = "renesas,r9a08g045-vbattb";
> > +        reg = <0x1005c000 0x1000>;
> > +        interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> > +        clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
> > +        clock-names = "bclk", "rtx";
> > +        #clock-cells = <1>;
> > +        power-domains = <&cpg>;
> > +        resets = <&cpg R9A08G045_VBAT_BRESETN>;
> > +        renesas,vbattb-load-nanofarads = <12500>;
> > +    };
> > -- 
> > 2.39.2
> >

Claudiu Beznea Sept. 2, 2024, 2:55 p.m. UTC | #3

On 31.08.2024 01:06, Alexandre Belloni wrote:
> On 30/08/2024 12:46:33-0500, Rob Herring wrote:
>> On Fri, Aug 30, 2024 at 04:02:07PM +0300, Claudiu wrote:
>>> From: Claudiu Beznea <[e-mail]>
>>>
>>> The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC,
>>> the tamper detector and a small general usage memory of 128B. Add
>>> documentation for it.
>>>
>>> Signed-off-by: Claudiu Beznea <[e-mail]>
>>> ---
>>>
>>> Changes in v3:
>>> - moved the file to clock dt bindings directory as it is the
>>>   only functionality supported at the moment; the other functionalities
>>>   (tamper detector, SRAM) are offered though register spreaded
>>>   though the address space of the VBATTB IP and not actually
>>>   individual devices; the other functionalities are not
>>>   planned to be supported soon and if they will be I think they
>>>   fit better on auxiliary bus than MFD
>>> - dropped interrupt names as requested in the review process
>>> - dropped the inner node for clock controller
>>> - added #clock-cells
>>> - added rtx clock
>>> - updated description for renesas,vbattb-load-nanofarads
>>> - included dt-bindings/interrupt-controller/irq.h in examples section
>>>
>>> Changes in v2:
>>> - changed file name and compatible
>>> - updated title, description sections
>>> - added clock controller part documentation and drop dedicated file
>>>   for it included in v1
>>> - used items to describe interrupts, interrupt-names, clocks, clock-names,
>>>   resets
>>> - dropped node labels and status
>>> - updated clock-names for clock controller to cope with the new
>>>   logic on detecting the necessity to setup bypass
>>>
>>>  .../clock/renesas,r9a08g045-vbattb.yaml       | 81 +++++++++++++++++++
>>>  1 file changed, 81 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml
>>> new file mode 100644
>>> index 000000000000..29df0e01fae5
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml
>>> @@ -0,0 +1,81 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/clock/renesas,r9a08g045-vbattb.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Renesas Battery Backup Function (VBATTB)
>>> +
>>> +description:
>>> +  Renesas VBATTB is an always on powered module (backed by battery) which
>>> +  controls the RTC clock (VBATTCLK), tamper detection logic and a small
>>> +  general usage memory (128B).
>>> +
>>> +maintainers:
>>> +  - Claudiu Beznea <[e-mail]>
>>> +
>>> +properties:
>>> +  compatible:
>>> +    const: renesas,r9a08g045-vbattb
>>> +
>>> +  reg:
>>> +    maxItems: 1
>>> +
>>> +  interrupts:
>>> +    items:
>>> +      - description: tamper detector interrupt
>>> +
>>> +  clocks:
>>> +    items:
>>> +      - description: VBATTB module clock
>>> +      - description: RTC input clock (crystal oscillator or external clock device)
>>> +
>>> +  clock-names:
>>> +    items:
>>> +      - const: bclk
>>> +      - const: rtx
>>> +
>>> +  '#clock-cells':
>>> +    const: 1
>>> +
>>> +  power-domains:
>>> +    maxItems: 1
>>> +
>>> +  resets:
>>> +    items:
>>> +      - description: VBATTB module reset
>>> +
>>> +  renesas,vbattb-load-nanofarads:
>>
>> Use defined units, don't add your own. So -picofarads should work for 
>> you.
> 
> We have a generic quartz-load-femtofarads property for RTCs which is
> what you define because the driver has VBATTB_XOSCCR_XSEL_4_PF which I
> guess is 4 pF which is 0.004 nF and 4000 fF.

I'll use this one in the next version.

Thank you for your review,
Claudiu Beznea

> 
>>
>>> +    description: load capacitance of the on board crystal oscillator
>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>> +    enum: [ 4000, 7000, 9000, 12500 ]
>>> +
>>> +required:
>>> +  - compatible
>>> +  - reg
>>> +  - interrupts
>>> +  - clocks
>>> +  - clock-names
>>> +  - '#clock-cells'
>>> +  - power-domains
>>> +  - resets
>>> +
>>> +additionalProperties: false
>>> +
>>> +examples:
>>> +  - |
>>> +    #include <dt-bindings/clock/r9a08g045-cpg.h>
>>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +    #include <dt-bindings/interrupt-controller/irq.h>
>>> +
>>> +    vbattb@1005c000 {
>>
>> clock-controller@...
>>
>>> +        compatible = "renesas,r9a08g045-vbattb";
>>> +        reg = <0x1005c000 0x1000>;
>>> +        interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
>>> +        clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
>>> +        clock-names = "bclk", "rtx";
>>> +        #clock-cells = <1>;
>>> +        power-domains = <&cpg>;
>>> +        resets = <&cpg R9A08G045_VBAT_BRESETN>;
>>> +        renesas,vbattb-load-nanofarads = <12500>;
>>> +    };
>>> -- 
>>> 2.39.2
>>>
>

Biju Das Sept. 3, 2024, 6:58 a.m. UTC | #4

Hi Claudiu,

> -----Original Message-----
> From: Claudiu <[e-mail]>
> Sent: Friday, August 30, 2024 2:02 PM
> Subject: [PATCH v3 01/12] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB
> 
> From: Claudiu Beznea <[e-mail]>
> 
> The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC, the tamper detector and a small
> general usage memory of 128B. Add documentation for it.
> 
> Signed-off-by: Claudiu Beznea <[e-mail]>
> ---
> 
> Changes in v3:
> - moved the file to clock dt bindings directory as it is the
>   only functionality supported at the moment; the other functionalities
>   (tamper detector, SRAM) are offered though register spreaded
>   though the address space of the VBATTB IP and not actually
>   individual devices; the other functionalities are not
>   planned to be supported soon and if they will be I think they
>   fit better on auxiliary bus than MFD
> - dropped interrupt names as requested in the review process
> - dropped the inner node for clock controller
> - added #clock-cells
> - added rtx clock
> - updated description for renesas,vbattb-load-nanofarads
> - included dt-bindings/interrupt-controller/irq.h in examples section
> 
> Changes in v2:
> - changed file name and compatible
> - updated title, description sections
> - added clock controller part documentation and drop dedicated file
>   for it included in v1
> - used items to describe interrupts, interrupt-names, clocks, clock-names,
>   resets
> - dropped node labels and status
> - updated clock-names for clock controller to cope with the new
>   logic on detecting the necessity to setup bypass
> 
>  .../clock/renesas,r9a08g045-vbattb.yaml       | 81 +++++++++++++++++++
>  1 file changed, 81 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml
> 
> diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml
> b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml
> new file mode 100644
> index 000000000000..29df0e01fae5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.y
> +++ aml
> @@ -0,0 +1,81 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/renesas,r9a08g045-vbattb.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas Battery Backup Function (VBATTB)
> +
> +description:
> +  Renesas VBATTB is an always on powered module (backed by battery)
> +which
> +  controls the RTC clock (VBATTCLK), tamper detection logic and a small
> +  general usage memory (128B).
> +
> +maintainers:
> +  - Claudiu Beznea <[e-mail]>
> +
> +properties:
> +  compatible:
> +    const: renesas,r9a08g045-vbattb
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    items:
> +      - description: tamper detector interrupt
> +
> +  clocks:
> +    items:
> +      - description: VBATTB module clock
> +      - description: RTC input clock (crystal oscillator or external
> + clock device)
> +
> +  clock-names:
> +    items:
> +      - const: bclk
> +      - const: rtx
> +
> +  '#clock-cells':
> +    const: 1
> +
> +  power-domains:
> +    maxItems: 1

Not sure, you need to document "PD_VBATT" power domain 
as per Table 41.2, this LSI supports 3 power domains(PD_ISOVCC, PD_VCC, PD_VBATT)

Power Mode PD_ISOVCC PD_VCC PD_VBATT
ALL_ON      ON          ON    ON
AWO         OFF         ON    ON
VBATT       OFF         OFF   ON
ALL_OFF     OFF         OFF   OFF

PD_VBATT domain is the area where the RTC/backup register is located, works on battery power when the power of
PD_VCC and PD_ISOVCC domain are turned off.

Cheers,
Biju

> +
> +  resets:
> +    items:
> +      - description: VBATTB module reset
> +
> +  renesas,vbattb-load-nanofarads:
> +    description: load capacitance of the on board crystal oscillator
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [ 4000, 7000, 9000, 12500 ]
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - clocks
> +  - clock-names
> +  - '#clock-cells'
> +  - power-domains
> +  - resets
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/r9a08g045-cpg.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +
> +    vbattb@1005c000 {
> +        compatible = "renesas,r9a08g045-vbattb";
> +        reg = <0x1005c000 0x1000>;
> +        interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> +        clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
> +        clock-names = "bclk", "rtx";
> +        #clock-cells = <1>;
> +        power-domains = <&cpg>;
> +        resets = <&cpg R9A08G045_VBAT_BRESETN>;
> +        renesas,vbattb-load-nanofarads = <12500>;
> +    };
> --
> 2.39.2
>

Geert Uytterhoeven Sept. 3, 2024, 7:23 a.m. UTC | #5

Hi Biju,

On Tue, Sep 3, 2024 at 8:58 AM Biju Das <[e-mail]> wrote:
> > -----Original Message-----
> > From: Claudiu <[e-mail]>
> > Sent: Friday, August 30, 2024 2:02 PM
> > Subject: [PATCH v3 01/12] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB
> >
> > From: Claudiu Beznea <[e-mail]>
> >
> > The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC, the tamper detector and a small
> > general usage memory of 128B. Add documentation for it.
> >
> > Signed-off-by: Claudiu Beznea <[e-mail]>

> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml
> > +  power-domains:
> > +    maxItems: 1
>
> Not sure, you need to document "PD_VBATT" power domain
> as per Table 41.2, this LSI supports 3 power domains(PD_ISOVCC, PD_VCC, PD_VBATT)
>
> Power Mode PD_ISOVCC PD_VCC PD_VBATT
> ALL_ON      ON          ON    ON
> AWO         OFF         ON    ON
> VBATT       OFF         OFF   ON
> ALL_OFF     OFF         OFF   OFF
>
> PD_VBATT domain is the area where the RTC/backup register is located, works on battery power when the power of
> PD_VCC and PD_ISOVCC domain are turned off.

AFAIU, PD_VBATT cannot be controlled by the user, and is just on
if main or battery power is supplied. So I don't think there is a need
to describe it in DT.

Gr{oetje,eeting}s,

                        Geert

Biju Das Sept. 3, 2024, 7:25 a.m. UTC | #6

Hi Geert,

> -----Original Message-----
> From: Geert Uytterhoeven <[e-mail]>
> Sent: Tuesday, September 3, 2024 8:23 AM
> Subject: Re: [PATCH v3 01/12] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB
> 
> Hi Biju,
> 
> On Tue, Sep 3, 2024 at 8:58 AM Biju Das <[e-mail]> wrote:
> > > -----Original Message-----
> > > From: Claudiu <[e-mail]>
> > > Sent: Friday, August 30, 2024 2:02 PM
> > > Subject: [PATCH v3 01/12] dt-bindings: clock:
> > > renesas,r9a08g045-vbattb: Document VBATTB
> > >
> > > From: Claudiu Beznea <[e-mail]>
> > >
> > > The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC,
> > > the tamper detector and a small general usage memory of 128B. Add documentation for it.
> > >
> > > Signed-off-by: Claudiu Beznea <[e-mail]>
> 
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbat
> > > +++ tb.yaml
> > > +  power-domains:
> > > +    maxItems: 1
> >
> > Not sure, you need to document "PD_VBATT" power domain as per Table
> > 41.2, this LSI supports 3 power domains(PD_ISOVCC, PD_VCC, PD_VBATT)
> >
> > Power Mode PD_ISOVCC PD_VCC PD_VBATT
> > ALL_ON      ON          ON    ON
> > AWO         OFF         ON    ON
> > VBATT       OFF         OFF   ON
> > ALL_OFF     OFF         OFF   OFF
> >
> > PD_VBATT domain is the area where the RTC/backup register is located,
> > works on battery power when the power of PD_VCC and PD_ISOVCC domain are turned off.
> 
> AFAIU, PD_VBATT cannot be controlled by the user, and is just on if main or battery power is supplied.
> So I don't think there is a need to describe it in DT.

OK, Just thought since DT is describing hardware, better to document this.

I am not an expert, So I agree with you.

Cheers,
Biju

Claudiu Beznea Sept. 3, 2024, 7:28 a.m. UTC | #7

On 03.09.2024 09:58, Biju Das wrote:
> Hi Claudiu,
> 
>> -----Original Message-----
>> From: Claudiu <[e-mail]>
>> Sent: Friday, August 30, 2024 2:02 PM
>> Subject: [PATCH v3 01/12] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB
>>
>> From: Claudiu Beznea <[e-mail]>
>>
>> The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC, the tamper detector and a small
>> general usage memory of 128B. Add documentation for it.
>>
>> Signed-off-by: Claudiu Beznea <[e-mail]>
>> ---
>>
>> Changes in v3:
>> - moved the file to clock dt bindings directory as it is the
>>   only functionality supported at the moment; the other functionalities
>>   (tamper detector, SRAM) are offered though register spreaded
>>   though the address space of the VBATTB IP and not actually
>>   individual devices; the other functionalities are not
>>   planned to be supported soon and if they will be I think they
>>   fit better on auxiliary bus than MFD
>> - dropped interrupt names as requested in the review process
>> - dropped the inner node for clock controller
>> - added #clock-cells
>> - added rtx clock
>> - updated description for renesas,vbattb-load-nanofarads
>> - included dt-bindings/interrupt-controller/irq.h in examples section
>>
>> Changes in v2:
>> - changed file name and compatible
>> - updated title, description sections
>> - added clock controller part documentation and drop dedicated file
>>   for it included in v1
>> - used items to describe interrupts, interrupt-names, clocks, clock-names,
>>   resets
>> - dropped node labels and status
>> - updated clock-names for clock controller to cope with the new
>>   logic on detecting the necessity to setup bypass
>>
>>  .../clock/renesas,r9a08g045-vbattb.yaml       | 81 +++++++++++++++++++
>>  1 file changed, 81 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml
>> b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml
>> new file mode 100644
>> index 000000000000..29df0e01fae5
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.y
>> +++ aml
>> @@ -0,0 +1,81 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/renesas,r9a08g045-vbattb.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Renesas Battery Backup Function (VBATTB)
>> +
>> +description:
>> +  Renesas VBATTB is an always on powered module (backed by battery)
>> +which
>> +  controls the RTC clock (VBATTCLK), tamper detection logic and a small
>> +  general usage memory (128B).
>> +
>> +maintainers:
>> +  - Claudiu Beznea <[e-mail]>
>> +
>> +properties:
>> +  compatible:
>> +    const: renesas,r9a08g045-vbattb
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +  interrupts:
>> +    items:
>> +      - description: tamper detector interrupt
>> +
>> +  clocks:
>> +    items:
>> +      - description: VBATTB module clock
>> +      - description: RTC input clock (crystal oscillator or external
>> + clock device)
>> +
>> +  clock-names:
>> +    items:
>> +      - const: bclk
>> +      - const: rtx
>> +
>> +  '#clock-cells':
>> +    const: 1
>> +
>> +  power-domains:
>> +    maxItems: 1
> 
> Not sure, you need to document "PD_VBATT" power domain 
> as per Table 41.2, this LSI supports 3 power domains(PD_ISOVCC, PD_VCC, PD_VBATT)
> 
> Power Mode PD_ISOVCC PD_VCC PD_VBATT
> ALL_ON      ON          ON    ON
> AWO         OFF         ON    ON
> VBATT       OFF         OFF   ON
> ALL_OFF     OFF         OFF   OFF
> 
> PD_VBATT domain is the area where the RTC/backup register is located, works on battery power when the power of
> PD_VCC and PD_ISOVCC domain are turned off.

In Linux, the CPG is the power domain provider for all the IPs in RZ/G3S
SoC (modeled though MSTOP CPG support). This is how it is currently
implemented.

Then groups of IPs are part of power domains PD_ISOVCC, PD_VCC, PD_VBATT.
These power domains are i2c controlled with the help of firmware (at least
at the moment).

From HW manual:
- PD_VCC domain always powered on area.

- PD_ISOVCC domain is the area where the power can be turned off.

- PD_VBATT domain is the area where the RTC/backup register is located,
  works on battery power when the power of
.

The power to these domains are controlled with the help of firmware. Linux
cannot do control itself as the CPU is in the PD_ISOVCC. If you look at
picture 41.3 Power mode transition [1] it is mentioned the relation b/w
these power domains (controlled by PMIC though firmware) and the supported
power saving modes: ALL_ON, AWO, VBATT.

Thank you,
Claudiu Beznea

[1] https://pasteboard.co/4ureEUnyCfV8.png

> 
> Cheers,
> Biju
> 
>> +
>> +  resets:
>> +    items:
>> +      - description: VBATTB module reset
>> +
>> +  renesas,vbattb-load-nanofarads:
>> +    description: load capacitance of the on board crystal oscillator
>> +    $ref: /schemas/types.yaml#/definitions/uint32
>> +    enum: [ 4000, 7000, 9000, 12500 ]
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - interrupts
>> +  - clocks
>> +  - clock-names
>> +  - '#clock-cells'
>> +  - power-domains
>> +  - resets
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/clock/r9a08g045-cpg.h>
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +    #include <dt-bindings/interrupt-controller/irq.h>
>> +
>> +    vbattb@1005c000 {
>> +        compatible = "renesas,r9a08g045-vbattb";
>> +        reg = <0x1005c000 0x1000>;
>> +        interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
>> +        clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
>> +        clock-names = "bclk", "rtx";
>> +        #clock-cells = <1>;
>> +        power-domains = <&cpg>;
>> +        resets = <&cpg R9A08G045_VBAT_BRESETN>;
>> +        renesas,vbattb-load-nanofarads = <12500>;
>> +    };
>> --
>> 2.39.2
>>
>

Biju Das Sept. 3, 2024, 7:29 a.m. UTC | #8

Hi Geert,

> -----Original Message-----
> From: Biju Das <[e-mail]>
> Sent: Tuesday, September 3, 2024 8:25 AM
> Subject: RE: [PATCH v3 01/12] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB
> 
> Hi Geert,
> 
> > -----Original Message-----
> > From: Geert Uytterhoeven <[e-mail]>
> > Sent: Tuesday, September 3, 2024 8:23 AM
> > Subject: Re: [PATCH v3 01/12] dt-bindings: clock:
> > renesas,r9a08g045-vbattb: Document VBATTB
> >
> > Hi Biju,
> >
> > On Tue, Sep 3, 2024 at 8:58 AM Biju Das <[e-mail]> wrote:
> > > > -----Original Message-----
> > > > From: Claudiu <[e-mail]>
> > > > Sent: Friday, August 30, 2024 2:02 PM
> > > > Subject: [PATCH v3 01/12] dt-bindings: clock:
> > > > renesas,r9a08g045-vbattb: Document VBATTB
> > > >
> > > > From: Claudiu Beznea <[e-mail]>
> > > >
> > > > The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for
> > > > RTC, the tamper detector and a small general usage memory of 128B. Add documentation for it.
> > > >
> > > > Signed-off-by: Claudiu Beznea <[e-mail]>
> >
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vb
> > > > +++ at
> > > > +++ tb.yaml
> > > > +  power-domains:
> > > > +    maxItems: 1
> > >
> > > Not sure, you need to document "PD_VBATT" power domain as per Table
> > > 41.2, this LSI supports 3 power domains(PD_ISOVCC, PD_VCC, PD_VBATT)
> > >
> > > Power Mode PD_ISOVCC PD_VCC PD_VBATT
> > > ALL_ON      ON          ON    ON
> > > AWO         OFF         ON    ON
> > > VBATT       OFF         OFF   ON
> > > ALL_OFF     OFF         OFF   OFF
> > >
> > > PD_VBATT domain is the area where the RTC/backup register is
> > > located, works on battery power when the power of PD_VCC and PD_ISOVCC domain are turned off.
> >
> > AFAIU, PD_VBATT cannot be controlled by the user, and is just on if main or battery power is
> supplied.

As per Figure 41.1 Power Domain and Power Supply,

If both PMIC PWS off, PD_VBATT is active, so looks like it is controllable
Outside Linux.

Cheers,
Biju

Biju Das Sept. 3, 2024, 7:36 a.m. UTC | #9

Hi Claudiu,

> -----Original Message-----
> From: claudiu beznea <[e-mail]>
> Sent: Tuesday, September 3, 2024 8:28 AM
> Subject: Re: [PATCH v3 01/12] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB
> 
> 
> 
> On 03.09.2024 09:58, Biju Das wrote:
> > Hi Claudiu,
> >
> >> -----Original Message-----
> >> From: Claudiu <[e-mail]>
> >> Sent: Friday, August 30, 2024 2:02 PM
> >> Subject: [PATCH v3 01/12] dt-bindings: clock:
> >> renesas,r9a08g045-vbattb: Document VBATTB
> >>
> >> From: Claudiu Beznea <[e-mail]>
> >>
> >> The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC,
> >> the tamper detector and a small general usage memory of 128B. Add documentation for it.
> >>
> >> Signed-off-by: Claudiu Beznea <[e-mail]>
> >> ---
> >>
> >> Changes in v3:
> >> - moved the file to clock dt bindings directory as it is the
> >>   only functionality supported at the moment; the other functionalities
> >>   (tamper detector, SRAM) are offered though register spreaded
> >>   though the address space of the VBATTB IP and not actually
> >>   individual devices; the other functionalities are not
> >>   planned to be supported soon and if they will be I think they
> >>   fit better on auxiliary bus than MFD
> >> - dropped interrupt names as requested in the review process
> >> - dropped the inner node for clock controller
> >> - added #clock-cells
> >> - added rtx clock
> >> - updated description for renesas,vbattb-load-nanofarads
> >> - included dt-bindings/interrupt-controller/irq.h in examples section
> >>
> >> Changes in v2:
> >> - changed file name and compatible
> >> - updated title, description sections
> >> - added clock controller part documentation and drop dedicated file
> >>   for it included in v1
> >> - used items to describe interrupts, interrupt-names, clocks, clock-names,
> >>   resets
> >> - dropped node labels and status
> >> - updated clock-names for clock controller to cope with the new
> >>   logic on detecting the necessity to setup bypass
> >>
> >>  .../clock/renesas,r9a08g045-vbattb.yaml       | 81 +++++++++++++++++++
> >>  1 file changed, 81 insertions(+)
> >>  create mode 100644
> >> Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml
> >>
> >> diff --git
> >> a/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.ya
> >> ml
> >> b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.ya
> >> ml
> >> new file mode 100644
> >> index 000000000000..29df0e01fae5
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbatt
> >> +++ b.y
> >> +++ aml
> >> @@ -0,0 +1,81 @@
> >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> >> +---
> >> +$id:
> >> +http://devicetree.org/schemas/clock/renesas,r9a08g045-vbattb.yaml#
> >> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >> +
> >> +title: Renesas Battery Backup Function (VBATTB)
> >> +
> >> +description:
> >> +  Renesas VBATTB is an always on powered module (backed by battery)
> >> +which
> >> +  controls the RTC clock (VBATTCLK), tamper detection logic and a
> >> +small
> >> +  general usage memory (128B).
> >> +
> >> +maintainers:
> >> +  - Claudiu Beznea <[e-mail]>
> >> +
> >> +properties:
> >> +  compatible:
> >> +    const: renesas,r9a08g045-vbattb
> >> +
> >> +  reg:
> >> +    maxItems: 1
> >> +
> >> +  interrupts:
> >> +    items:
> >> +      - description: tamper detector interrupt
> >> +
> >> +  clocks:
> >> +    items:
> >> +      - description: VBATTB module clock
> >> +      - description: RTC input clock (crystal oscillator or external
> >> + clock device)
> >> +
> >> +  clock-names:
> >> +    items:
> >> +      - const: bclk
> >> +      - const: rtx
> >> +
> >> +  '#clock-cells':
> >> +    const: 1
> >> +
> >> +  power-domains:
> >> +    maxItems: 1
> >
> > Not sure, you need to document "PD_VBATT" power domain as per Table
> > 41.2, this LSI supports 3 power domains(PD_ISOVCC, PD_VCC, PD_VBATT)
> >
> > Power Mode PD_ISOVCC PD_VCC PD_VBATT
> > ALL_ON      ON          ON    ON
> > AWO         OFF         ON    ON
> > VBATT       OFF         OFF   ON
> > ALL_OFF     OFF         OFF   OFF
> >
> > PD_VBATT domain is the area where the RTC/backup register is located,
> > works on battery power when the power of PD_VCC and PD_ISOVCC domain are turned off.
> 
> In Linux, the CPG is the power domain provider for all the IPs in RZ/G3S SoC (modeled though MSTOP CPG
> support). This is how it is currently implemented.
> 
> Then groups of IPs are part of power domains PD_ISOVCC, PD_VCC, PD_VBATT.
> These power domains are i2c controlled with the help of firmware (at least at the moment).
> 
> From HW manual:
> - PD_VCC domain always powered on area.
> 
> - PD_ISOVCC domain is the area where the power can be turned off.
> 
> - PD_VBATT domain is the area where the RTC/backup register is located,
>   works on battery power when the power of .
> 
> The power to these domains are controlled with the help of firmware. Linux cannot do control itself as
> the CPU is in the PD_ISOVCC. If you look at picture 41.3 Power mode transition [1] it is mentioned the
> relation b/w these power domains (controlled by PMIC though firmware) and the supported power saving
> modes: ALL_ON, AWO, VBATT.
> 

DT describes hardware. So, the question was, from that perspective, do we need to document PD_VBATT domain,
as it can be controlled outside linux??

Cheers,
Biju

Geert Uytterhoeven Sept. 3, 2024, 7:40 a.m. UTC | #10

Hi Biju,

On Tue, Sep 3, 2024 at 9:36 AM Biju Das <[e-mail]> wrote:
> > -----Original Message-----
> > From: claudiu beznea <[e-mail]>
> > Sent: Tuesday, September 3, 2024 8:28 AM
> > Subject: Re: [PATCH v3 01/12] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB
> >
> > On 03.09.2024 09:58, Biju Das wrote:
> > >> -----Original Message-----
> > >> From: Claudiu <[e-mail]>
> > >> Sent: Friday, August 30, 2024 2:02 PM
> > >> Subject: [PATCH v3 01/12] dt-bindings: clock:
> > >> renesas,r9a08g045-vbattb: Document VBATTB
> > >>
> > >> From: Claudiu Beznea <[e-mail]>
> > >>
> > >> The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC,
> > >> the tamper detector and a small general usage memory of 128B. Add documentation for it.
> > >>
> > >> Signed-off-by: Claudiu Beznea <[e-mail]>
> > >> ---
> > >>
> > >> Changes in v3:
> > >> - moved the file to clock dt bindings directory as it is the
> > >>   only functionality supported at the moment; the other functionalities
> > >>   (tamper detector, SRAM) are offered though register spreaded
> > >>   though the address space of the VBATTB IP and not actually
> > >>   individual devices; the other functionalities are not
> > >>   planned to be supported soon and if they will be I think they
> > >>   fit better on auxiliary bus than MFD
> > >> - dropped interrupt names as requested in the review process
> > >> - dropped the inner node for clock controller
> > >> - added #clock-cells
> > >> - added rtx clock
> > >> - updated description for renesas,vbattb-load-nanofarads
> > >> - included dt-bindings/interrupt-controller/irq.h in examples section
> > >>
> > >> Changes in v2:
> > >> - changed file name and compatible
> > >> - updated title, description sections
> > >> - added clock controller part documentation and drop dedicated file
> > >>   for it included in v1
> > >> - used items to describe interrupts, interrupt-names, clocks, clock-names,
> > >>   resets
> > >> - dropped node labels and status
> > >> - updated clock-names for clock controller to cope with the new
> > >>   logic on detecting the necessity to setup bypass
> > >>
> > >>  .../clock/renesas,r9a08g045-vbattb.yaml       | 81 +++++++++++++++++++
> > >>  1 file changed, 81 insertions(+)
> > >>  create mode 100644
> > >> Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml
> > >>
> > >> diff --git
> > >> a/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.ya
> > >> ml
> > >> b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.ya
> > >> ml
> > >> new file mode 100644
> > >> index 000000000000..29df0e01fae5
> > >> --- /dev/null
> > >> +++ b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbatt
> > >> +++ b.y
> > >> +++ aml
> > >> @@ -0,0 +1,81 @@
> > >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > >> +---
> > >> +$id:
> > >> +http://devicetree.org/schemas/clock/renesas,r9a08g045-vbattb.yaml#
> > >> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > >> +
> > >> +title: Renesas Battery Backup Function (VBATTB)
> > >> +
> > >> +description:
> > >> +  Renesas VBATTB is an always on powered module (backed by battery)
> > >> +which
> > >> +  controls the RTC clock (VBATTCLK), tamper detection logic and a
> > >> +small
> > >> +  general usage memory (128B).
> > >> +
> > >> +maintainers:
> > >> +  - Claudiu Beznea <[e-mail]>
> > >> +
> > >> +properties:
> > >> +  compatible:
> > >> +    const: renesas,r9a08g045-vbattb
> > >> +
> > >> +  reg:
> > >> +    maxItems: 1
> > >> +
> > >> +  interrupts:
> > >> +    items:
> > >> +      - description: tamper detector interrupt
> > >> +
> > >> +  clocks:
> > >> +    items:
> > >> +      - description: VBATTB module clock
> > >> +      - description: RTC input clock (crystal oscillator or external
> > >> + clock device)
> > >> +
> > >> +  clock-names:
> > >> +    items:
> > >> +      - const: bclk
> > >> +      - const: rtx
> > >> +
> > >> +  '#clock-cells':
> > >> +    const: 1
> > >> +
> > >> +  power-domains:
> > >> +    maxItems: 1
> > >
> > > Not sure, you need to document "PD_VBATT" power domain as per Table
> > > 41.2, this LSI supports 3 power domains(PD_ISOVCC, PD_VCC, PD_VBATT)
> > >
> > > Power Mode PD_ISOVCC PD_VCC PD_VBATT
> > > ALL_ON      ON          ON    ON
> > > AWO         OFF         ON    ON
> > > VBATT       OFF         OFF   ON
> > > ALL_OFF     OFF         OFF   OFF
> > >
> > > PD_VBATT domain is the area where the RTC/backup register is located,
> > > works on battery power when the power of PD_VCC and PD_ISOVCC domain are turned off.
> >
> > In Linux, the CPG is the power domain provider for all the IPs in RZ/G3S SoC (modeled though MSTOP CPG
> > support). This is how it is currently implemented.
> >
> > Then groups of IPs are part of power domains PD_ISOVCC, PD_VCC, PD_VBATT.
> > These power domains are i2c controlled with the help of firmware (at least at the moment).
> >
> > From HW manual:
> > - PD_VCC domain always powered on area.
> >
> > - PD_ISOVCC domain is the area where the power can be turned off.
> >
> > - PD_VBATT domain is the area where the RTC/backup register is located,
> >   works on battery power when the power of .
> >
> > The power to these domains are controlled with the help of firmware. Linux cannot do control itself as
> > the CPU is in the PD_ISOVCC. If you look at picture 41.3 Power mode transition [1] it is mentioned the
> > relation b/w these power domains (controlled by PMIC though firmware) and the supported power saving
> > modes: ALL_ON, AWO, VBATT.
>
> DT describes hardware. So, the question was, from that perspective, do we need to document PD_VBATT domain,
> as it can be controlled outside linux??

No, as it is controlled by an external entity, outside the system you
are describing.

DT also doesn't describe external power input, power switches, power cords,
low/medium/high voltage circuit breakers, nuclear power plants, the Sun, ...

Gr{oetje,eeting}s,

                        Geert

Claudiu Beznea Sept. 3, 2024, 7:44 a.m. UTC | #11

On 03.09.2024 10:36, Biju Das wrote:
> Hi Claudiu,
> 
>> -----Original Message-----
>> From: claudiu beznea <[e-mail]>
>> Sent: Tuesday, September 3, 2024 8:28 AM
>> Subject: Re: [PATCH v3 01/12] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB
>>
>>
>>
>> On 03.09.2024 09:58, Biju Das wrote:
>>> Hi Claudiu,
>>>
>>>> -----Original Message-----
>>>> From: Claudiu <[e-mail]>
>>>> Sent: Friday, August 30, 2024 2:02 PM
>>>> Subject: [PATCH v3 01/12] dt-bindings: clock:
>>>> renesas,r9a08g045-vbattb: Document VBATTB
>>>>
>>>> From: Claudiu Beznea <[e-mail]>
>>>>
>>>> The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC,
>>>> the tamper detector and a small general usage memory of 128B. Add documentation for it.
>>>>
>>>> Signed-off-by: Claudiu Beznea <[e-mail]>
>>>> ---
>>>>
>>>> Changes in v3:
>>>> - moved the file to clock dt bindings directory as it is the
>>>>   only functionality supported at the moment; the other functionalities
>>>>   (tamper detector, SRAM) are offered though register spreaded
>>>>   though the address space of the VBATTB IP and not actually
>>>>   individual devices; the other functionalities are not
>>>>   planned to be supported soon and if they will be I think they
>>>>   fit better on auxiliary bus than MFD
>>>> - dropped interrupt names as requested in the review process
>>>> - dropped the inner node for clock controller
>>>> - added #clock-cells
>>>> - added rtx clock
>>>> - updated description for renesas,vbattb-load-nanofarads
>>>> - included dt-bindings/interrupt-controller/irq.h in examples section
>>>>
>>>> Changes in v2:
>>>> - changed file name and compatible
>>>> - updated title, description sections
>>>> - added clock controller part documentation and drop dedicated file
>>>>   for it included in v1
>>>> - used items to describe interrupts, interrupt-names, clocks, clock-names,
>>>>   resets
>>>> - dropped node labels and status
>>>> - updated clock-names for clock controller to cope with the new
>>>>   logic on detecting the necessity to setup bypass
>>>>
>>>>  .../clock/renesas,r9a08g045-vbattb.yaml       | 81 +++++++++++++++++++
>>>>  1 file changed, 81 insertions(+)
>>>>  create mode 100644
>>>> Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml
>>>>
>>>> diff --git
>>>> a/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.ya
>>>> ml
>>>> b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.ya
>>>> ml
>>>> new file mode 100644
>>>> index 000000000000..29df0e01fae5
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbatt
>>>> +++ b.y
>>>> +++ aml
>>>> @@ -0,0 +1,81 @@
>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
>>>> +---
>>>> +$id:
>>>> +http://devicetree.org/schemas/clock/renesas,r9a08g045-vbattb.yaml#
>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>> +
>>>> +title: Renesas Battery Backup Function (VBATTB)
>>>> +
>>>> +description:
>>>> +  Renesas VBATTB is an always on powered module (backed by battery)
>>>> +which
>>>> +  controls the RTC clock (VBATTCLK), tamper detection logic and a
>>>> +small
>>>> +  general usage memory (128B).
>>>> +
>>>> +maintainers:
>>>> +  - Claudiu Beznea <[e-mail]>
>>>> +
>>>> +properties:
>>>> +  compatible:
>>>> +    const: renesas,r9a08g045-vbattb
>>>> +
>>>> +  reg:
>>>> +    maxItems: 1
>>>> +
>>>> +  interrupts:
>>>> +    items:
>>>> +      - description: tamper detector interrupt
>>>> +
>>>> +  clocks:
>>>> +    items:
>>>> +      - description: VBATTB module clock
>>>> +      - description: RTC input clock (crystal oscillator or external
>>>> + clock device)
>>>> +
>>>> +  clock-names:
>>>> +    items:
>>>> +      - const: bclk
>>>> +      - const: rtx
>>>> +
>>>> +  '#clock-cells':
>>>> +    const: 1
>>>> +
>>>> +  power-domains:
>>>> +    maxItems: 1
>>>
>>> Not sure, you need to document "PD_VBATT" power domain as per Table
>>> 41.2, this LSI supports 3 power domains(PD_ISOVCC, PD_VCC, PD_VBATT)
>>>
>>> Power Mode PD_ISOVCC PD_VCC PD_VBATT
>>> ALL_ON      ON          ON    ON
>>> AWO         OFF         ON    ON
>>> VBATT       OFF         OFF   ON
>>> ALL_OFF     OFF         OFF   OFF
>>>
>>> PD_VBATT domain is the area where the RTC/backup register is located,
>>> works on battery power when the power of PD_VCC and PD_ISOVCC domain are turned off.
>>
>> In Linux, the CPG is the power domain provider for all the IPs in RZ/G3S SoC (modeled though MSTOP CPG
>> support). This is how it is currently implemented.
>>
>> Then groups of IPs are part of power domains PD_ISOVCC, PD_VCC, PD_VBATT.
>> These power domains are i2c controlled with the help of firmware (at least at the moment).
>>
>> From HW manual:
>> - PD_VCC domain always powered on area.
>>
>> - PD_ISOVCC domain is the area where the power can be turned off.
>>
>> - PD_VBATT domain is the area where the RTC/backup register is located,
>>   works on battery power when the power of .
>>
>> The power to these domains are controlled with the help of firmware. Linux cannot do control itself as
>> the CPU is in the PD_ISOVCC. If you look at picture 41.3 Power mode transition [1] it is mentioned the
>> relation b/w these power domains (controlled by PMIC though firmware) and the supported power saving
>> modes: ALL_ON, AWO, VBATT.
>>
> 
> DT describes hardware. So, the question was, from that perspective, do we need to document PD_VBATT domain,
> as it can be controlled outside linux??

The control to these domains is passed to firmware.

From my point of view these will never be used by Linux becuase:
- the PD_ISOVCC is where the CPU resides and it cannot cut itself its power
- the PD_VCC is a domain where critical IPs like CPG, SYSC resides
- the VBATT is where the RTC resides, RTC that should stay on forever

Should we document something that will be never used?

> 
> Cheers,
> Biju

Biju Das Sept. 3, 2024, 7:51 a.m. UTC | #12

Hi Claudiu,

> -----Original Message-----
> From: claudiu beznea <[e-mail]>
> Sent: Tuesday, September 3, 2024 8:44 AM
> Subject: Re: [PATCH v3 01/12] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB
> 
> 
> 
> On 03.09.2024 10:36, Biju Das wrote:
> > Hi Claudiu,
> >
> >> -----Original Message-----
> >> From: claudiu beznea <[e-mail]>
> >> Sent: Tuesday, September 3, 2024 8:28 AM
> >> Subject: Re: [PATCH v3 01/12] dt-bindings: clock:
> >> renesas,r9a08g045-vbattb: Document VBATTB
> >>
> >>
> >>
> >> On 03.09.2024 09:58, Biju Das wrote:
> >>> Hi Claudiu,
> >>>
> >>>> -----Original Message-----
> >>>> From: Claudiu <[e-mail]>
> >>>> Sent: Friday, August 30, 2024 2:02 PM
> >>>> Subject: [PATCH v3 01/12] dt-bindings: clock:
> >>>> renesas,r9a08g045-vbattb: Document VBATTB
> >>>>
> >>>> From: Claudiu Beznea <[e-mail]>
> >>>>
> >>>> The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC,
> >>>> the tamper detector and a small general usage memory of 128B. Add documentation for it.
> >>>>
> >>>> Signed-off-by: Claudiu Beznea <[e-mail]>
> >>>> ---
> >>>>
> >>>> Changes in v3:
> >>>> - moved the file to clock dt bindings directory as it is the
> >>>>   only functionality supported at the moment; the other functionalities
> >>>>   (tamper detector, SRAM) are offered though register spreaded
> >>>>   though the address space of the VBATTB IP and not actually
> >>>>   individual devices; the other functionalities are not
> >>>>   planned to be supported soon and if they will be I think they
> >>>>   fit better on auxiliary bus than MFD
> >>>> - dropped interrupt names as requested in the review process
> >>>> - dropped the inner node for clock controller
> >>>> - added #clock-cells
> >>>> - added rtx clock
> >>>> - updated description for renesas,vbattb-load-nanofarads
> >>>> - included dt-bindings/interrupt-controller/irq.h in examples
> >>>> section
> >>>>
> >>>> Changes in v2:
> >>>> - changed file name and compatible
> >>>> - updated title, description sections
> >>>> - added clock controller part documentation and drop dedicated file
> >>>>   for it included in v1
> >>>> - used items to describe interrupts, interrupt-names, clocks, clock-names,
> >>>>   resets
> >>>> - dropped node labels and status
> >>>> - updated clock-names for clock controller to cope with the new
> >>>>   logic on detecting the necessity to setup bypass
> >>>>
> >>>>  .../clock/renesas,r9a08g045-vbattb.yaml       | 81 +++++++++++++++++++
> >>>>  1 file changed, 81 insertions(+)
> >>>>  create mode 100644
> >>>> Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.ya
> >>>> ml
> >>>>
> >>>> diff --git
> >>>> a/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.
> >>>> ya
> >>>> ml
> >>>> b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.
> >>>> ya
> >>>> ml
> >>>> new file mode 100644
> >>>> index 000000000000..29df0e01fae5
> >>>> --- /dev/null
> >>>> +++ b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vba
> >>>> +++ tt
> >>>> +++ b.y
> >>>> +++ aml
> >>>> @@ -0,0 +1,81 @@
> >>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML
> >>>> +1.2
> >>>> +---
> >>>> +$id:
> >>>> +http://devicetree.org/schemas/clock/renesas,r9a08g045-vbattb.yaml#
> >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>>> +
> >>>> +title: Renesas Battery Backup Function (VBATTB)
> >>>> +
> >>>> +description:
> >>>> +  Renesas VBATTB is an always on powered module (backed by
> >>>> +battery) which
> >>>> +  controls the RTC clock (VBATTCLK), tamper detection logic and a
> >>>> +small
> >>>> +  general usage memory (128B).
> >>>> +
> >>>> +maintainers:
> >>>> +  - Claudiu Beznea <[e-mail]>
> >>>> +
> >>>> +properties:
> >>>> +  compatible:
> >>>> +    const: renesas,r9a08g045-vbattb
> >>>> +
> >>>> +  reg:
> >>>> +    maxItems: 1
> >>>> +
> >>>> +  interrupts:
> >>>> +    items:
> >>>> +      - description: tamper detector interrupt
> >>>> +
> >>>> +  clocks:
> >>>> +    items:
> >>>> +      - description: VBATTB module clock
> >>>> +      - description: RTC input clock (crystal oscillator or
> >>>> + external clock device)
> >>>> +
> >>>> +  clock-names:
> >>>> +    items:
> >>>> +      - const: bclk
> >>>> +      - const: rtx
> >>>> +
> >>>> +  '#clock-cells':
> >>>> +    const: 1
> >>>> +
> >>>> +  power-domains:
> >>>> +    maxItems: 1
> >>>
> >>> Not sure, you need to document "PD_VBATT" power domain as per Table
> >>> 41.2, this LSI supports 3 power domains(PD_ISOVCC, PD_VCC, PD_VBATT)
> >>>
> >>> Power Mode PD_ISOVCC PD_VCC PD_VBATT
> >>> ALL_ON      ON          ON    ON
> >>> AWO         OFF         ON    ON
> >>> VBATT       OFF         OFF   ON
> >>> ALL_OFF     OFF         OFF   OFF
> >>>
> >>> PD_VBATT domain is the area where the RTC/backup register is
> >>> located, works on battery power when the power of PD_VCC and PD_ISOVCC domain are turned off.
> >>
> >> In Linux, the CPG is the power domain provider for all the IPs in
> >> RZ/G3S SoC (modeled though MSTOP CPG support). This is how it is currently implemented.
> >>
> >> Then groups of IPs are part of power domains PD_ISOVCC, PD_VCC, PD_VBATT.
> >> These power domains are i2c controlled with the help of firmware (at least at the moment).
> >>
> >> From HW manual:
> >> - PD_VCC domain always powered on area.
> >>
> >> - PD_ISOVCC domain is the area where the power can be turned off.
> >>
> >> - PD_VBATT domain is the area where the RTC/backup register is located,
> >>   works on battery power when the power of .
> >>
> >> The power to these domains are controlled with the help of firmware.
> >> Linux cannot do control itself as the CPU is in the PD_ISOVCC. If you
> >> look at picture 41.3 Power mode transition [1] it is mentioned the
> >> relation b/w these power domains (controlled by PMIC though firmware)
> >> and the supported power saving
> >> modes: ALL_ON, AWO, VBATT.
> >>
> >
> > DT describes hardware. So, the question was, from that perspective, do
> > we need to document PD_VBATT domain, as it can be controlled outside linux??
> 
> The control to these domains is passed to firmware.
> 
> From my point of view these will never be used by Linux becuase:
> - the PD_ISOVCC is where the CPU resides and it cannot cut itself its power
> - the PD_VCC is a domain where critical IPs like CPG, SYSC resides
> - the VBATT is where the RTC resides, RTC that should stay on forever
> 
> Should we document something that will be never used?

If it is inside the system, you are describing to avoid ABI breakages any future.

Eg [1], there are interrupts we documented, Don't know we will ever use it in linux.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml#n58

Cheers,
Biju

Geert Uytterhoeven Oct. 10, 2024, 9:58 a.m. UTC | #13

Hi Claudiu,

On Fri, Aug 30, 2024 at 3:02 PM Claudiu <[e-mail]> wrote:
> From: Claudiu Beznea <[e-mail]>
>
> The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC,
> the tamper detector and a small general usage memory of 128B. Add
> documentation for it.
>
> Signed-off-by: Claudiu Beznea <[e-mail]>
> ---
>
> Changes in v3:
> - moved the file to clock dt bindings directory as it is the
>   only functionality supported at the moment; the other functionalities
>   (tamper detector, SRAM) are offered though register spreaded
>   though the address space of the VBATTB IP and not actually
>   individual devices; the other functionalities are not
>   planned to be supported soon and if they will be I think they
>   fit better on auxiliary bus than MFD
> - dropped interrupt names as requested in the review process
> - dropped the inner node for clock controller
> - added #clock-cells
> - added rtx clock
> - updated description for renesas,vbattb-load-nanofarads
> - included dt-bindings/interrupt-controller/irq.h in examples section

Thanks for the update!

LGTM, modulo issues pointed out in other review comments.

Gr{oetje,eeting}s,

                        Geert

Geert Uytterhoeven Oct. 10, 2024, 10:08 a.m. UTC | #14

Hi Claudiu,

On Fri, Aug 30, 2024 at 3:02 PM Claudiu <[e-mail]> wrote:
> From: Claudiu Beznea <[e-mail]>
>
> The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC,
> the tamper detector and a small general usage memory of 128B. Add
> documentation for it.
>
> Signed-off-by: Claudiu Beznea <[e-mail]>
> ---
>
> Changes in v3:
> - moved the file to clock dt bindings directory as it is the
>   only functionality supported at the moment; the other functionalities
>   (tamper detector, SRAM) are offered though register spreaded
>   though the address space of the VBATTB IP and not actually
>   individual devices; the other functionalities are not
>   planned to be supported soon and if they will be I think they
>   fit better on auxiliary bus than MFD

The battery-backed-up SRAM could be exported through the
NVMEM framework. I am not sure it offers some way to export the tamper
flag (to indicate it's erased, i.e. empty).

Gr{oetje,eeting}s,

                        Geert

Patch

diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml
new file mode 100644
index 000000000000..29df0e01fae5
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml
@@ -0,0 +1,81 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,r9a08g045-vbattb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas Battery Backup Function (VBATTB)
+
+description:
+  Renesas VBATTB is an always on powered module (backed by battery) which
+  controls the RTC clock (VBATTCLK), tamper detection logic and a small
+  general usage memory (128B).
+
+maintainers:
+  - Claudiu Beznea <[e-mail]>
+
+properties:
+  compatible:
+    const: renesas,r9a08g045-vbattb
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: tamper detector interrupt
+
+  clocks:
+    items:
+      - description: VBATTB module clock
+      - description: RTC input clock (crystal oscillator or external clock device)
+
+  clock-names:
+    items:
+      - const: bclk
+      - const: rtx
+
+  '#clock-cells':
+    const: 1
+
+  power-domains:
+    maxItems: 1
+
+  resets:
+    items:
+      - description: VBATTB module reset
+
+  renesas,vbattb-load-nanofarads:
+    description: load capacitance of the on board crystal oscillator
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [ 4000, 7000, 9000, 12500 ]
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - '#clock-cells'
+  - power-domains
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/r9a08g045-cpg.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    vbattb@1005c000 {
+        compatible = "renesas,r9a08g045-vbattb";
+        reg = <0x1005c000 0x1000>;
+        interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
+        clock-names = "bclk", "rtx";
+        #clock-cells = <1>;
+        power-domains = <&cpg>;
+        resets = <&cpg R9A08G045_VBAT_BRESETN>;
+        renesas,vbattb-load-nanofarads = <12500>;
+    };