| Message ID | 20240830215701.103262-3-marex@denx.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/3] ARM: dts: stm32: Sort properties in audio endpoints on STM32MP15xx DHCOM PDK2 | expand |
Hi Marek On 8/30/24 23:56, Marek Vasut wrote: > By default the SGTL5000 derives bit and frame clock from MCLK, which > does not produce particularly accurate results. The SGTL5000 PLL does > improve the accuracy, but also increases power consumption. Using the > SoC SAI interface as bit and frame clock source results in the best > accuracy without the power consumption increase downside. Switch the > bit and frame clock direction from SAI to SGTL5000, reduce mclk-fs to > match. > > Signed-off-by: Marek Vasut <marex@denx.de> > --- > Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> > Cc: Conor Dooley <conor+dt@kernel.org> > Cc: Krzysztof Kozlowski <krzk+dt@kernel.org> > Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> > Cc: Rob Herring <robh@kernel.org> > Cc: devicetree@vger.kernel.org > Cc: kernel@dh-electronics.com > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-stm32@st-md-mailman.stormreply.com > --- > arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) 3 PHDK2 patches applied on stm32-next. Thanks Alex
diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi index ea933da64903c..171d7c7658fa8 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi @@ -191,15 +191,11 @@ sgtl5000_port: port { sgtl5000_tx_endpoint: endpoint@0 { reg = <0>; - bitclock-master; - frame-master; remote-endpoint = <&sai2a_endpoint>; }; sgtl5000_rx_endpoint: endpoint@1 { reg = <1>; - bitclock-master; - frame-master; remote-endpoint = <&sai2b_endpoint>; }; }; @@ -245,10 +241,12 @@ sai2a: audio-controller@4400b004 { sai2a_port: port { sai2a_endpoint: endpoint { remote-endpoint = <&sgtl5000_tx_endpoint>; + bitclock-master; dai-format = "i2s"; dai-tdm-slot-num = <2>; dai-tdm-slot-width = <16>; - mclk-fs = <512>; + frame-master; + mclk-fs = <256>; }; }; }; @@ -263,10 +261,12 @@ sai2b: audio-controller@4400b024 { sai2b_port: port { sai2b_endpoint: endpoint { remote-endpoint = <&sgtl5000_rx_endpoint>; + bitclock-master; dai-format = "i2s"; dai-tdm-slot-num = <2>; dai-tdm-slot-width = <16>; - mclk-fs = <512>; + frame-master; + mclk-fs = <256>; }; }; };
By default the SGTL5000 derives bit and frame clock from MCLK, which does not produce particularly accurate results. The SGTL5000 PLL does improve the accuracy, but also increases power consumption. Using the SoC SAI interface as bit and frame clock source results in the best accuracy without the power consumption increase downside. Switch the bit and frame clock direction from SAI to SGTL5000, reduce mclk-fs to match. Signed-off-by: Marek Vasut <marex@denx.de> --- Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Conor Dooley <conor+dt@kernel.org> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com --- arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)