| Message ID | 1725503468-22105-4-git-send-email-hongxing.zhu@nxp.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add one clock gate for i.MX95 HSIO block | expand |
On Thu, Sep 05, 2024 at 10:31:08AM +0800, Richard Zhu wrote: > CREF_EN (Bit6) of LFAST_IO_REG control i.MX95 PCIe REF clock out > enable/disable. > > Add compatible string "fsl,imx95-hsio-blk-ctl" to support PCIe REF clock > out gate. > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > --- Reviewed-by: Frank Li <Frank.Li@nxp.com> > drivers/clk/imx/clk-imx95-blk-ctl.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c b/drivers/clk/imx/clk-imx95-blk-ctl.c > index 74f595f9e5e3..596dfb2f3b75 100644 > --- a/drivers/clk/imx/clk-imx95-blk-ctl.c > +++ b/drivers/clk/imx/clk-imx95-blk-ctl.c > @@ -248,6 +248,25 @@ static const struct imx95_blk_ctl_dev_data dispmix_csr_dev_data = { > .clk_reg_offset = 0, > }; > > +static const struct imx95_blk_ctl_clk_dev_data hsio_blk_ctl_clk_dev_data[] = { > + [0] = { > + .name = "hsio_blk_ctl_clk", > + .parent_names = (const char *[]){ "hsio_pll", }, > + .num_parents = 1, > + .reg = 0, > + .bit_idx = 6, > + .bit_width = 1, > + .type = CLK_GATE, > + .flags = CLK_SET_RATE_PARENT, > + } > +}; > + > +static const struct imx95_blk_ctl_dev_data hsio_blk_ctl_dev_data = { > + .num_clks = 1, > + .clk_dev_data = hsio_blk_ctl_clk_dev_data, > + .clk_reg_offset = 0, > +}; > + > static int imx95_bc_probe(struct platform_device *pdev) > { > struct device *dev = &pdev->dev; > @@ -418,6 +437,7 @@ static const struct of_device_id imx95_bc_of_match[] = { > { .compatible = "nxp,imx95-display-master-csr", }, > { .compatible = "nxp,imx95-lvds-csr", .data = &lvds_csr_dev_data }, > { .compatible = "nxp,imx95-display-csr", .data = &dispmix_csr_dev_data }, > + { .compatible = "nxp,imx95-hsio-blk-ctl", .data = &hsio_blk_ctl_dev_data }, > { .compatible = "nxp,imx95-vpu-csr", .data = &vpublk_dev_data }, > { /* Sentinel */ }, > }; > -- > 2.37.1 >
> Subject: [PATCH v2 3/3] clk: imx95-blk-ctl: Add one clock gate for HSIO > block > > CREF_EN (Bit6) of LFAST_IO_REG control i.MX95 PCIe REF clock out > enable/disable. > > Add compatible string "fsl,imx95-hsio-blk-ctl" to support PCIe REF clock Typo: nxp,imx95-hsio-blk-ctl. Except this, LGTM: Reviewed-by: Peng Fan <peng.fan@nxp.com> Regards, Peng.
> -----Original Message----- > From: Peng Fan <peng.fan@nxp.com> > Sent: 2024年9月5日 16:06 > To: Hongxing Zhu <hongxing.zhu@nxp.com>; robh@kernel.org; > krzk+dt@kernel.org; conor+dt@kernel.org; abelvesa@kernel.org; > mturquette@baylibre.com; sboyd@kernel.org; shawnguo@kernel.org; > s.hauer@pengutronix.de; festevam@gmail.com > Cc: devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; > linux-arm-kernel@lists.infradead.org; linux-clk@vger.kernel.org; > imx@lists.linux.dev; kernel@pengutronix.de; Hongxing Zhu > <hongxing.zhu@nxp.com> > Subject: RE: [PATCH v2 3/3] clk: imx95-blk-ctl: Add one clock gate for HSIO > block > > > Subject: [PATCH v2 3/3] clk: imx95-blk-ctl: Add one clock gate for > > HSIO block > > > > CREF_EN (Bit6) of LFAST_IO_REG control i.MX95 PCIe REF clock out > > enable/disable. > > > > Add compatible string "fsl,imx95-hsio-blk-ctl" to support PCIe REF > > clock > > Typo: nxp,imx95-hsio-blk-ctl. Nice catch, thanks. Would be corrected later. Best Regards Richard Zhu > > Except this, LGTM: Reviewed-by: Peng Fan <peng.fan@nxp.com> > > Regards, > Peng.
diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c b/drivers/clk/imx/clk-imx95-blk-ctl.c index 74f595f9e5e3..596dfb2f3b75 100644 --- a/drivers/clk/imx/clk-imx95-blk-ctl.c +++ b/drivers/clk/imx/clk-imx95-blk-ctl.c @@ -248,6 +248,25 @@ static const struct imx95_blk_ctl_dev_data dispmix_csr_dev_data = { .clk_reg_offset = 0, }; +static const struct imx95_blk_ctl_clk_dev_data hsio_blk_ctl_clk_dev_data[] = { + [0] = { + .name = "hsio_blk_ctl_clk", + .parent_names = (const char *[]){ "hsio_pll", }, + .num_parents = 1, + .reg = 0, + .bit_idx = 6, + .bit_width = 1, + .type = CLK_GATE, + .flags = CLK_SET_RATE_PARENT, + } +}; + +static const struct imx95_blk_ctl_dev_data hsio_blk_ctl_dev_data = { + .num_clks = 1, + .clk_dev_data = hsio_blk_ctl_clk_dev_data, + .clk_reg_offset = 0, +}; + static int imx95_bc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -418,6 +437,7 @@ static const struct of_device_id imx95_bc_of_match[] = { { .compatible = "nxp,imx95-display-master-csr", }, { .compatible = "nxp,imx95-lvds-csr", .data = &lvds_csr_dev_data }, { .compatible = "nxp,imx95-display-csr", .data = &dispmix_csr_dev_data }, + { .compatible = "nxp,imx95-hsio-blk-ctl", .data = &hsio_blk_ctl_dev_data }, { .compatible = "nxp,imx95-vpu-csr", .data = &vpublk_dev_data }, { /* Sentinel */ }, };
CREF_EN (Bit6) of LFAST_IO_REG control i.MX95 PCIe REF clock out enable/disable. Add compatible string "fsl,imx95-hsio-blk-ctl" to support PCIe REF clock out gate. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> --- drivers/clk/imx/clk-imx95-blk-ctl.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)